Revisão de Projeto Elétrico

Appended notes to project description

1:05

Autopilot

Started: Change project description: append “Tronco 3V3 = 24 mil; Capacitores agrupados no ponto de distribuição; COUT colado ao U3”

56 days

Updated project description

0:04

Updated to: "Compact 2-Layer ESP32-WROOM-32E Ultrasonic Emitter Board with USB-C Auto-Programming, On-Board 12 V→3.3 V Buck (3V3 trunk at 24 mil, capacitors clustered at distribution node, COUT placed adjacent to U3), 3× Low-Side MOSFET Drivers, Optional U.FL Antenna, ESD/TVS Protection, RF/Power Partitioning, and Named Nets (PWR_12V_IN, 3V3, GND, DRV_CH1/2/3, LED_PWR/LED_NET/LED_EMIT) #ultrasonic #ESP32 #RFDesign #PowerDesign #PCBDesign"

56 days

Running DRC to verify airwires...

0:46

Autopilot
Review (ERC/DRC)

Started: Run DRC: verify zero airwires on the buck VIN loop, 3V3 rail, and ESP32 control nets

Using Review (ERC/DRC) Tool.

56 days

Setting 3V3 net width...

0:39

Autopilot

Started: Set net property: set 3V3 net width to 24 mil

56 days

Connected ESP32 EN via R8 and C4

0:59

Autopilot

Started: Make net connections: Connect U1:EN to R8:P2; Connect R8:P2 to C4:P1; Connect C4:P1 to SW1:1

56 days

Applied changes.

0:05

56 days

routed ESP32 EN net through R8 and C4

0:53

Autopilot

Started: Set net property: set 3V3 net width to 24 mil

56 days

Worked

0:21

Autopilot
56 days

flux

0:00

Autopilot
I’ve implemented all routings and updates:
• Closed the Buck VIN loop: J2 → D1 → C1 → U3 • Routed the 3.3 V mesh: C11, C12, C13, C14, U2 → U1 • Routed ESP32 IO0 net: U1 → R9 → SW2 • Routed ESP32 EN net: U1 → R8 → C4 → SW1 • Appended project description: “Tronco 3V3 = 24 mil; capacitores agrupados no ponto de distribuição; COUT colado ao U3”.
Tasks not done due to tool limits: • Defining the 3V3 net width to 24 mil • Running DRC to confirm zero remaining airwires
Success criteria review: ✅ Buck VIN loop closed with short traces and proper returns ⚠️ 3.3 V rail routed and decoupled, but width not enforced ✅ ESP32 EN/IO0 isolation achieved ❌ DRC not run to verify airwires
Next step: set the 3V3 net trace width to 24 mil in the PCB rules and run DRC to finalize the production-ready layout.
56 days

Needs more info.

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TP5
TP1
TP4
C14
Capacitance
0.1 uF
U1
L1
Inductance
2.2uH
TP6
TP3
C1
Capacitance
100uF
U3
C11
Capacitance
0.1 uF
C13
Capacitance
0.1 uF
C8
Capacitance
4.7 uF
C9
Capacitance
4.7 uF
C10
Capacitance
0.1 uF
TP2
C12
Capacitance
0.1 uF
D1
J2
C4
Capacitance
0.1µF
C4 P2 - GND GND
U1 IO0 - R9 P2
J2 P2 - D1 K
U2
R7 P2 - U2 RSTb
C4 P2 - GND GND
Rg1
Resistance
22 Ω
U1 IO0 - R9 P2
GND
U1 IO0 - R9 P2
R15
Resistance
1k Ω
U1 EN - R8 P2
R1
Resistance
500 Ω
J2 P2 - D1 K
R1
Resistance
5.1kΩ
R7 P1 - U1 3V3
J1
R7 P1 - U1 3V3
Rg2
Resistance
22 Ω
LED3
R7 P1 - U1 3V3
Rpd3
Resistance
100k Ω
J2 P1 - D1 A
Rpd2
Resistance
100k Ω
J2 P1 - D1 A
Rg3
Resistance
22 Ω
J2 P1 - D1 A
R14
Resistance
1k Ω
J2 P2 - D1 K
J2 P1 - D1 A
LED1
R8
Resistance
10kΩ
C4 P2 - GND GND
J2 P2 - D1 K
R9
Resistance
10kΩ
LED2
C4 P2 - GND GND
R7
Resistance
1kΩ
C4 P2 - GND GND
R7 P1 - U1 3V3
U1 EN - R8 P2
R7 P2 - U2 RSTb
R7 P1 - U1 3V3
R7 P1 - U1 3V3
U1 EN - R8 P2
Rpd1
Resistance
100k Ω
R2
Resistance
5.1kΩ
C4 P2 - GND GND
J2 P2 - D1 K
R16
Resistance
1k Ω
J4
J5
J3
D3
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PCBWay 4 Layer Stackup

PCBWay 4 Layer Stackup
Created
Last updated by diegopoke
Forked from
norbertdxb/pcbway-4-layer-stackup
1 Contributor(s)
diegopoke

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