• VMID_DIV = 3V3A × R15/(R14+R15); nominal 0.5 × 3V3A. Divider Thevenin resistance 50k and C22 1uF give 50ms time constant / 3.18Hz pole before buffer dynamics. Actual VMID includes U4A offset/loading/finite bandwidth. Opposite ±0.1% divider extremes yield ratio 0.4995–0.5005 under the recorded targets, not a certified production band.
• R1/C5 alone give 1/(2π×10×10uF)=1.59kHz; actual shunt includes C6/C12/C13/C21/C29/C31 and load impedances, so use the full supply network. DC 3V3A = 3V3 − 10ohm × analog-load current. Supply current modeled implicitly by ideal voltage-controlled sources is generally zero and cannot reproduce that drop.
• U3 RG = R12 + R13 = 27.4k gives G1 = 4.6496350365. Preserve RG midpoint loading. Low-impedance source approximation gives input attenuation 10M/(10M + 200k) = 0.980392157 per balanced leg; skin impedance changes this. R10/R11 terminate at VMID, not ground.
• C18 plus equal C19/C20 has approximate differential effective C =47pF+10pF/2=52pF; differential series R≈400k gives RF pole ≈7.65kHz. Approximate common-mode RC pole 1/(2π×200k×10pF)=79.6kHz. Electrode impedance, bias resistors, clamp capacitance and board/cable parasitics modify these approximations. Do not substitute these poles for the actual connected network.
• HP C23/R16: 19.75Hz and 8.06ms nominal. At DC C23 opens, so HP_NODE returns to VMID; the INA can still saturate before this capacitor. High-pass filtering does not rescue an overloaded first stage.
• J4 open: R19 dead-ended at GAIN_SEL, G2 = 1 + 210k/10k = 22; ideal total G1×G2 = 102.291970803. J4 closed: R19 joins VMID, Rg = 10k ∥ 2.43k, G2 = 108.4197530864; total = 504.112282599. The user authorized this gain redistribution, not a guaranteed signal/noise envelope; 8 kS/s remains a planned sample rate. J4 is manual and unreadable by firmware in this hardware. Model finite shunt resistance only as a declared study assumption until sourced.
• Each LP section is unity-gain Sallen-Key with input -> Ra -> node A -> Rb -> node B -> follower output, Cf from A to output, Cg from B to GND. Ideal denominator is 1+s·Cg(Ra+Rb)+s²RaRbCfCg. Thus f0=1/[2π√(RaRbCfCg)] and Q=√(RaRbCfCg)/[Cg(Ra+Rb)]. LP1 explicitly uses Ra=R20, Rb=R21, Cf=C24, Cg=C25, giving f0≈506Hz, Q≈0.5477. LP2 uses Ra=R22, Rb=R23, Cf=C26, Cg=C27, giving f0≈505Hz, Q≈1.3056. Target Butterworth section Qs were 0.5412/1.3066; actual LP1 is not exactly that target. They are not two Q=0.707 sections. C24/C26 do not go to ground.
• For equal-R sections, Q≈0.5√(Cf/Cg): cap-ratio errors change peaking; common scaling of both caps moves f0 without changing Q. Frequency logarithmic sensitivity is −1/2 to each of Ra/Rb/Cf/Cg. Use the general Q equation when independently varying resistors. HP has −1 logarithmic sensitivity to each R16/C23. Gain changes follow resistor ratios, including INA internal gain accuracy separately from external RG tolerance.
• R24/C28 alone yield 100ns and 1.59MHz, not an extra 500Hz anti-alias pole. The reservoir/kickback settling must be simulated with the ADC switch and opamp output impedance, not inferred from this corner alone.
• RLD feedback relative to VMID: H(s)=−(R26/R25)/(1+sR26C30), nominal DC −20.04, feedback pole 15.92Hz, high-frequency integration-unity estimate 1/(2πR25C30)=318.95Hz. This is not actual body-loop crossover. R27+R28=400k limits drive but adds load-dependent loop phase. U5A buffer dynamics and U3 CM_SENSE transfer must remain in the loop.
• VBUS sense divider R3/R31 gives 2/3 nominal: 3.167–3.500V if protected 5V_USB itself is 4.75–5.25V. F1 drop lowers it. R31 lacks recorded tolerance, so a guaranteed divider min/max cannot be calculated. Earlier design notes' opposite 1% R31 calculation is an assumption, not supported by that property. No positive-injection/ramp guarantee follows from this ratio.

1. Topology/linear check: ideal resistors/capacitors and ideal amplifiers, finite testbench bias paths, a declared ideal 3V3A supply and VMID divider/buffer. Useful for nominal transfer only. Explicitly exclude rail limits, offset, noise, output current, ADC kickback, supply drop, chopper behavior, ESD and RLD safety. Do not use a single differential-output behavioral INA with floating RG pins to analyze RLD.
2. Behavioral study: finite open-loop gain, dominant pole, output resistance, swing/current/ slew limits and offsets, with assumptions listed. The older RLD study used a single-pole 5.5MHz opamp assumption; that is not a full OPA4340 vendor macromodel or guaranteed worst-case GBW. A behavioral INA must implement the physical split-RG common-mode path. Compare CM_SENSE versus external common mode and differential input before trusting loop gain. Do not hardwire CM_SENSE to an arbitrary constant merely to obtain convergence.
3. Vendor-model validation: TI datasheet states an OPA4340 SPICE macromodel is available. Catalog search on 2026-10-27 identified OPAx340 TINA-TI model Rev E, SBOM273E and INA333 PSpice Rev G SBOM382G / TINA-TI Rev E SBOM310E. These are catalog listings, not downloaded, version-pinned, inspected or executed model assets in this project. Model body revision/date/hash, license, simulator compatibility and exact pin order remain TBD; do not equate ZIP revision to the internal model revision. Download from TI, retain original archive and hash, record .SUBCKT headers/port mapping and any syntax adaptations before use. A single-channel family model may be instantiated eight times for U4/U5, but shared-supply/channel coupling must then be declared excluded unless supported. No quad-specific crosstalk simulation is claimed.

• Default exploratory manufacturing draws: independent per part, including nominally identical resistors/caps, unless a matched network or vendor ratio-tracking specification exists. Notes saying “matched” for R6/R8, R7/R9, R10/R11, R12/R13, R14/R15 and C19/C20 express design intent, not guaranteed correlation. These are discrete parts, not a selected matched array.
• Study both independent worst mismatch and a separately labelled common-lot/common-temperature component. Positive correlation can preserve ratios yet move absolute poles. Shared ambient temperature is correlated; self-heating and local gradients need separate assumptions. Keep supply/VMID/reference variations coupled physically, not independent random voltage sources.
• Corner R12+R13 sum for INA gain; corner their mismatch and parasitic loading for CM_SENSE. Independently vary R17/R18/R19 and both J4 states. Sweep R14/R15 opposite extremes for midpoint ratio. Sweep R6–R11/C19/C20/electrode imbalance for CM-to-differential conversion. RLD tolerance includes R25, R26, C30 and both output limiters.
• Sweep LP cap ratio and resistor mismatch, not only all-high/all-low frequency corners; the high-Q second section is particularly sensitive to ratio/GBW and load effects. Calculate actual f0/Q per draw, along with combined passband peak/ripple and attenuation. Tolerance corners are not guaranteed bounded system response if active parameters are omitted.
• Include per-amplifier Vos, Ib±/Ios, voltage/current noise spectra, finite GBW/open-loop poles, output rail/current limits and INA gain/CMRR errors only with sourced conditional values or explicit TBD study ranges. Same-die offsets/drift are not guaranteed independent; compare shared/common and independent study cases when covariance is unknown. Never equate typical curves to absolute bounds. Noise is a time/frequency stochastic process, not simply a random DC offset.
• Save random seed, sample count, distribution/ranges/provenance, temperature, supplies, electrode conditions, model hashes, simulator/options and failure logs. Increase sample count until reported quantiles stabilize to a stated study criterion; do not invent a production-yield confidence from an arbitrary run count. Report convergence failures separately, not as good draws.

1. Operating point/startup: power ramps, 3V3A load drop, divider/VMID settling, C23 charge history and both gains; plot every amplifier output, INA inputs, CM_SENSE, RLD current and ADC bias. Initial capacitor voltages must be declared. Allow enough settling relative to slowest time constant; prior firmware plan discards at least 1s, not a proven worst-case recovery bound.
2. AC transfer: differential excitation through finite electrode impedances, normalize to the stated source point (skin/body or jack, never interchange them). Record gain at 20/100/500Hz, peak, relative −3dB corners, f0/Q, 4kHz and 7.5kHz attenuation and phase. Repeat RLD on/off, both gains, tolerances and rails. Do not force common mode with a stiff ideal source when measuring RLD effectiveness.
3. Electrode/skin/cable: explicitly draw a body common-mode node; each sensing electrode gets its own interface impedance and DC half-cell source; reference electrode gets its own impedance to RLD_JACK. A simple Rs+(Rp||Cp) or R||C is an exploratory equivalent, not a validated biological model. Prior setup used 50k||47nF per electrode, 200pF cable, then 500pF cables and 200k||10nF electrode cases. Reuse only as labelled prior study cases; broader min/max, frequency-dependent skin parameters, contact mismatch, cable-to-ground/interconductor capacitance, shield termination, electrode area, motion and noise sources are TBD measurements/study inputs. A cable length does not fix capacitance. Sweep one lead and all leads independently, open/near-short contacts, asymmetric half-cell offsets, dry/high impedance and cable capacitance. Do not assume all cable capacitance goes to local board ground; define its actual return.
4. RLD loop stability: measure return ratio using an injection method preserving DC bias/loading, with correct feedback polarity; include U3 midpoint transfer, U5A/B, limiters, electrode/body/cable paths, input RF caps, bias resistors and clamp capacitance. Record crossover(s), phase/gain margin and probe sign convention; look for multiple crossings. Repeat electrode/cable and component/GBW/rail corners, lead-open/reconnection, U5 saturation and recovery. Closed-loop transient ringing is corroboration, not a substitute for a valid loop measurement. Acceptance margins are design targets TBD, not already certified.
5. Signal/DC/headroom: sweep differential offset through −100/0/+100mV as earlier design study cases, plus amplitudes around 1mVpk and previous 15mVpk low-gain/3mVpk high-gain trials. These are not confirmed user range requirements. Sweep common mode independently and inspect INA internal/headroom limits where model exposes them; increase offsets/amplitude until saturation, then remove to measure recovery. HP recentering does not prove INA linearity. Include overload artifact and mismatch-induced CM conversion.
6. Mains/interference: 50Hz and 60Hz common-mode coupling via explicitly declared capacitance/current source; independently vary coupling asymmetry, body return and cable paths. Prior 1Vpk through 2pF is a behavioral testbench condition, not a real-world environment limit. Report body CM, input differential artifact, ADC residual and RLD-on/off comparison. Add differential mains and out-of-band tones; ranges are TBD. Avoid reporting the RLD-only suppression ratio as the total circuit CMRR.
7. ADC load/aliasing: start with ideal high-Z ADC, then switched sample capacitor with sourced or labelled assumed capacitance/switch resistance, acquisition time, charge injection, reference impedance and sample timing. Sweep source load and opamp stability, verify R24/C28 settling within a declared fraction-of-LSB target (target TBD), and include parasitic cable/board loads only where physically applicable. At provisional 8kS/s Nyquist=4kHz; inject tones near n·fs±20…500Hz and integrate broadband out-of-band noise through analog response and sampling. Analog attenuation alone is not a complete alias budget: source amplitude/spectrum and acceptable aliased noise are TBD. Compare ADC time-domain sampled spectra, not only continuous AC plots. Clock jitter and actual reference noise require separate sourced inputs.
8. Noise/thermal/leakage: include resistor thermal noise, electrode impedances, R10/R11 noise/loading, opamp/INA voltage and current noise, clamp leakage and VMID/reference noise; integrate over a clearly stated analog/digital bandwidth. Add low-frequency drift/offset separately from broadband noise. Vendor-model .noise support must be demonstrated rather than assumed. Noise targets and temperature extremes remain unconfirmed.

• R6/R7/R8/R9 thermal sources sit in their own series legs and are shaped by C18–C20, R10/R11, electrode impedances and the INA input path before HP/gain/LP. R10/R11 have substantial impedance but their noise is shunted by the actual source network; do not simply RSS their open-circuit 10M noise at the INA. R12/R13 inject through the internal gain-resistor network and CM_SENSE/RLD loop; they are not external input series resistors. Validate that the INA model propagates this noise physically.
• U3 input voltage/current noise needs spectra valid at current G1 ≈ 4.65, actual supply, common mode and temperature. Input-current noise flows through frequency-dependent impedances seen separately by VIN+ and VIN−; a shortcut i_n×200k misses the electrodes, 10M returns, RF caps, RLD and mismatch. Include any separate INA output-noise term with the correct gain dependence if the vendor model/specification separates input and output noise. Conditional device spectra and 1/f corners remain incomplete; earlier G≈11 lumped estimates and headline design-note numbers are not adopted as current board-level guarantees.
• R16 thermal noise and U4B input noise enter at/near HP_NODE or GAIN_FB; they need their own transfer rather than assumed suppression by C23/R16's signal high pass. R17/R18 and R19 when J4 is closed contribute through the feedback impedances. U4B voltage-noise gain generally differs from signal transfer versus frequency. For J4 open, R19 is ideally dead-ended but its real parasitic path may matter at high frequency; label parasitics separately.
• R20/R21 and U4C voltage/current noise act inside LP1. R22/R23 and U4D noise act inside LP2, and R24 thermal noise is generated after the two LP sections. Thus not every source is filtered by the full fourth-order response. Include C28, opamp output impedance and ADC loading in their transfers; ideal capacitors are noiseless, while modeled ESR is a dissipative noise source. Model dielectric loss only with sourced or labelled assumed parameters.
• R14/R15 thermal sources are filtered by C22 then U4A. U4A's own noise is not filtered by C22 identically. VMID noise fans out simultaneously to U3 REF, R10/R11, R16/R18/J4 and U5 references. Keep this as a shared source with multiple coherent paths, not independent copies to RSS. U5A/B noise and R25/R26/R27/R28 thermal noise feed back through the reference electrode/body into sensing electrodes; common-mode conversion depends on mismatch. U5C/D may contribute shared-rail loading/coupling if the model supports it; independent channel models otherwise exclude that effect explicitly.
• U2/input-source noise, R1 thermal noise, supply-current modulation and local ground/reference noise require actual PSRR/reference-path models. A 3V3A fluctuation simultaneously moves VMID, INA/opamp supplies and ADC VREF; ratiometric cancellation may be partial and frequency-dependent. Do not inject independent noise at every one of these derived nodes or claim perfect cancellation. R2/R3/R29/R30/R31 and other digital-side components may be excluded from an ideal analog-only noise solve only with supply/ground coupling explicitly excluded; in a coupled model their contributions enter via physical paths, not a fabricated direct signal connection.

Python
# Pseudocode: substitute actual simulator APIs; no numerical board result implied.
snapshot = build_exact_78_part_connectivity_from_inventory()
assert snapshot.connected_net_count == 49
inputs = require_or_label_assumed(
    temperature_K, signal_rms_and_PSD, electrode_models_and_noise,
    supply_reference_PSD, device_noise_models, ADC_and_digital_filter)
audit_noise_ownership()  # exactly once: native resistor, vendor model, or external source
for gain_state in ['J4_open', 'J4_closed']:
    circuit = set_physical_shunt(snapshot, gain_state)
    for corner_or_MC_draw in declared_parameter_cases:
        apply_parameters(circuit, corner_or_MC_draw)
        op = solve_DC_and_startup(circuit, electrodes, body_return)
        require_stable_loop_and_unclipped_all_stages(op)
        f = frequency_grid_resolving_HP_LP_RLD_and_noise_corners()
        Hsig = AC_transfer(circuit, differential_source_plane, 'ADC_EMG', f)
        primitives, S_cross = define_noise_sources_and_cross_PSD(f, inputs)
        # Each primitive is injected once, allowing every physical shared path.
        H = [unit_voltage_or_current_transfer(circuit, src, 'ADC_EMG', f)
             for src in primitives]
        Sout = sum(H[j] * conj(H[k]) * S_cross[j,k]
                   for j in primitives for k in primitives)
        require_real_nonnegative_PSD_within_numerical_error(Sout)
        noise_20_500 = sqrt(integrate(Sout, 20, 500))
        noise_full = sqrt(integrate(Sout, declared_low, converged_high))
        signal_out = sqrt(integrate(abs(Hsig)**2 * Ssignal, signal_band))
        report_per_source_powers_and_cross_terms_and_ENBWs()
        sampled_noise = fold_aliases_with_aperture_and_digital_filter(Sout, fs)
        # Add ADC error only under proven ownership/correlation assumptions.
        sampled_wave = transient_sample_and_quantize_with_actual_Vref(
            circuit, signal_plus_noise_and_separate_interference_cases)
        assert_no_clipping_and_check_PSD_normalization(sampled_wave)
        report_SNR_SINAD_and_headroom_for_defined_band_and_signal()
save_all_seeds_models_assumptions_integration_limits_and_convergence_failures()

• Tolerance/model completeness: 22 R/C tolerance properties missing (list above); remaining generic tolerance/dielectric targets need MPN-backed qualification. R4/R5 absolute resistance, selected capacitor effective-C/ESR/aging data, resistor TCR, INA/opamp noise/offset/GBW/rail corners and their distribution/correlation remain incomplete. This blocks guaranteed statistical yield and production bounds, not a labelled nominal topology simulation.
• Vendor models: candidate TI model archives identified but not fetched/hashed/inspected; RG midpoint fidelity and parameter/noise coverage unverified. This blocks calling a future run vendor-model validated until checked. Package-property gaps on U4/U5/J1 and crystal CL discrepancy require confirmation before physical release; BOM descriptions are not footprint audits.
• Exact external USB isolator: make/model, power and data isolation ratings/classification, barrier capacitance/leakage, output voltage/current capacity, inrush/foldback, FS throughput, shield continuity, creepage/clearance and alternate grounds unknown. A provisional 60mA budget is not isolator qualification. Human connection is blocked.
• Cable: SparkFun CAB-12970 is only the prior candidate (three surface snaps/TRS). Exact purchased model/contact-to-color map and impedance/capacitance/shield model remain unconfirmed. Continuity-map each cable tip=EMG+, ring=EMG−, sleeve=REF; no audio mating or needle-electrode compatibility. Insert/remove only with pads detached from a person. Its product links in prior records are supplemental, not a verified electrical cable model.
• Performance requirements: confirmed passband target is 20–500Hz; input signal amplitude, differential/common-mode offset envelope, input impedance, noise/SNR, gain accuracy, rejection, overload recovery and alias-error targets are unconfirmed. Gain ~100/500 and 8kS/s remain provisional defaults. Numeric unsupplied ranges in this guide are TBD or explicitly study assumptions, never facts.
• Before layout: board dimensions/shape, mounting, connector edge positions/access, enclosure/height/keepouts, environmental/temperature and isolation-distance requirements are unresolved. Firmware build, actual ADC timing, clock load/startup, PCB parasitics, procurement, assembly, bench validation and manufacturing release are separate work.