Electrical capture finished: 78 components, 49 nets, including USB Type-C, a protected surface-electrode input, instrumentation amplifier, high-pass/gain/low-pass chain, driven reference, STM32F401 and support circuitry. No PCB placement/routing, firmware image, manufacturing release or human-use qualification is complete. This record distinguishes schematic facts, calculations, ideal simulations and unverified real-world limits.

This is a design-stage BOM, not a procurement release; generic parts still need final MPN selection and qualification.

User rule: 0402 wherever practical; larger only when needed. Of 62 R/C components, 48 are 0402. Exceptions:

The capture used ideal signal-chain amplifiers and a single-pole behavioral op-amp model for driven-reference stability. No vendor macro-models, tolerance Monte Carlo, ESD model or hardware measurements were used.

At +100 mV differential DC electrode offset, the ideal model gives INA_OUT about 2.73 V and ADC bias 1.650 V after settling; tested 15 mVpk low-gain / 3 mVpk high-gain inputs stayed near 0.2–3.1 V output. The reported combined |offset + AC signal| limit of about 145 mV is calculated using ideal rail/headroom assumptions. INA333 input-common-mode/output envelope at 3.3 V and actual analog supply drop remain bench-validation items. Do not claim these input ranges across supply, temperature, leakage and component variation without testing.

CM_SENSE -> U5A buffer -> U5B inversion around VMID using R25=49.9 kOhm, R26=1 MOhm in parallel with C30=10 nF -> R27/R28=200 kOhm each -> J1 sleeve. D5 clamps the resistor midpoint to analog rails. Feedback DC gain about -20 and pole about 15.9 Hz, calculated. Spare U5 channels are closed-loop followers at VMID.

The nominal simulated setup gave about 30.6 dB common-mode reduction at 60 Hz; this is setup-dependent, not a universal CMRR claim. An open reference lead can rail the amplifier; there is no dedicated hardware lead-off detector. Verify lead-open recovery, real electrode/cable variation, clamp leakage and common-mode conversion from finite bias impedance and resistor mismatch. Raising C30 from 4.7 to 10 nF traded some common-mode suppression for stability margin.

For a conservative 5.25 V local fault, ignoring clamp assistance and using the actual 1% limiter tolerances:

These are engineering allowances, not a completed datasheet-worst-case budget. No sleep mode is defined, so sleep current is unverified. Actual firmware/temperature/per-part maxima must be qualified before final power-path release.

The LDO reflects output current approximately 1:1 to input; rounded miscellaneous allowance includes divider, CC and regulator overhead rather than a verified per-part quiescent sum. At 60 mA, calculated LDO dissipation is (5.25-3.3) x 0.06 = 0.117 W before detailed thermal analysis. At 3.5 Ohm recorded PTC resistance, drop is 0.21 V; minimum protected input is about 4.54 V from 4.75 V. F1 temperature derating, isolator output current/inrush/foldback and LDO thermal performance still need confirmation. Do not infer a 3 A USB allowance from Type-C: the present design budgets less than 100 mA and does not read high-current advertisement.

Candidate SparkFun CAB-12970, a documented 3.5 mm three-conductor-to-three-snap surface-pad cable. Sources previously inspected: product sheet, product page. Exact color/contact map is unpublished in that material. Verify and label tip=EMG+, ring=EMG-, sleeve=REF for every cable. Sleeve is NOT ground. Never connect audio equipment, never claim needle compatibility, and insert/remove only with electrodes detached from a person.

Review the captured electrical design; then optionally draw the readable schematic (about 35–45 minutes and roughly 30 ACU for this size), build acquisition firmware, or set physical board constraints and proceed to PCB placement. Drafting and layout are not performed automatically in this turn.