The connectivity comparison confirms that all 49 nets still connect the same pins. The readability check found more work in the op-amp stages and electrode-jack wiring, which I’m correcting now.
The analog stages now have drawn signal paths, but a wire-placement bug on flipped symbols is blocking part of the USB drawing. I’ll leave the affected connections labeled and finish the independent label fixes; the bug needs Contact Support.
I arranged all 78 components into eight functional blocks and added local wires and net labels. All 49 nets retain exactly the same pin connections; no electrical connections changed.
The drawing is not fully clean: wire crossings and label crowding remain, and a flipped-symbol wire-placement bug blocks the shared USB power wire. That bug needs Contact Support; the remaining drafting cleanup is still open.
Status: Draft electrical capture complete, with documented verification limits. A single-channel surface-EMG acquisition board captures bipolar muscle signals using STM32F401CEU6. This is not a human-ready or fabrication-ready instrument. The 78-component, 49-net circuit uses INA333AIDGKR, two OPA4340UA quad amplifiers, TPS7A2033PDBVR regulation, and a 12 MHz crystal; firmware remains unimplemented. Final ERC has zero errors and one justified D4 library-metadata warning. See Design Notes for the complete record.
Intended Use
Surface-electrode research prototype. First validation uses a signal/electrode simulator only. Human connection is blocked pending qualified electrical safety review of the complete isolated system. No invasive, diagnostic, clinical, defibrillator or electrosurgery use.
What the Device Should Do
Acquire differential muscle activity without rectifying it, reject DC electrode offset after low-gain instrumentation amplification, limit out-of-band content, and stream sampled data to a host.
Main Features
Three-snap electrode cable through a 3.5 mm TRS jack.
Protected differential input with bias-current return paths.
Compensated, current-limited driven reference.
Approximate 20–500 Hz analog passband; selectable gain around 100/500.
STM32F401 ADC at an 8 kS/s target and USB Full Speed recording link.
Mechanical System Architecture
Electronics-first bare-board prototype; no enclosure is included at this phase. Surface pads connect through a detachable three-snap cable; external USB isolator sits between board and host. PCB dimensions, mountings, and enclosure remain deferred until electrical capture is reviewed.
Electrical System Architecture
Diagram
Hardware Subsystems
Input: source-verified jack and low-leakage protection; no direct electrode-to-ground connection. Analog: low-gain INA333-class stage, input common-mode/output-envelope review, buffered 1.65 V reference, first-order HP, selectable gain and fourth-order Butterworth LP (section Q approximately 0.5412 and 1.3066). Driven reference: buffered common-mode sensing, negative feedback about midrail, compensated loop, redundant series output limiting. Compute: supported STM32F401 variant with proper supply/VCAP/boot/reset/SWD/clock connections. Record exact choices in Design Notes during capture.
Interfaces and Connections
User-confirmed jack decision (2026-10-27): retain SJ-3524-SMT-TR and omit GPIO plug detection. Tip (pin 2) is EMG+, ring (pin 3) is EMG−, sleeve (pin 1) is driven reference, and the tip-switch contact (pin 4) remains unconnected. No jack replacement or GPIO detector is planned.
Electrode jack: tip EMG+, ring EMG-, sleeve driven reference, NOT ground.
Cable candidate: SparkFun CAB-12970, three surface snaps. Contact-to-color assignment must be continuity-verified and labelled; no hot insertion on a person and no audio equipment mating.
USB: Type-C receptacle, USB 2.0 Full Speed device/sink, independent 5.1 kOhm CC1/CC2 pulldowns, no PD or high-current advertisement assumption. Isolated 5 V and data are supplied by an external isolator; exact model and ratings still required before human use.
SWD/debug/other instruments: bench only with electrodes disconnected unless independently verified isolation preserves the complete safety boundary.
Power and Runtime Expectations
External isolated USB power, no battery or charger. Local 3.3 V supply and filtered analog rail; output centered around 1.65 V. No battery runtime target. Keep total load compatible with the actual isolator output and USB enumeration budget.
Power Tree and Power Budget
Diagram
The provisional allowance is 35 mA typical / 60 mA design load at USB, with calculated maximum-budget LDO dissipation about 0.117 W at 5.25 V. This is not a completed datasheet-worst-case budget; see Design Notes for the per-load allowances and qualification gaps. Input now includes F1 resettable fuse between VBUS_CONN and 5V_USB; USB data protection and a limited-coordination VBUS clamp are captured. The actual isolator capacity, inrush and fault behavior remain unknown.
Manufacturing and Assembly Expectations
Prefer LCSC-available active parts. Use 0402 passives wherever practical; larger sizes only for effective capacitance, precision/dielectric availability, fault voltage/energy or other documented requirements. User explicitly requires USB Type-C. Layer count, PCB assembly and fabrication exports are deferred. No manufacturing release without final MPN selection, footprint verification and DRC.
Firmware-Relevant Hardware Requirements
8 kS/s timer-triggered ADC with DMA; adequate ADC acquisition time for source impedance. USB device streaming with sequence numbers and gain metadata. Raw bipolar signal is represented by ADC samples around midpoint. SWD, stable boot defaults, reset and USB-compatible clock required. Firmware implementation is not part of initial capture.
Physical Design Expectations
Keep electrode analog inputs distant from USB/digital clocks and supply noise; place protection at connector, maintain short matched high-impedance paths and low-impedance analog reference. Dimensions and connector edge placement are later layout decisions.
Important Design Decisions
Use modest initial gain to preserve electrode-offset headroom. On 2026-10-27 the user authorized R12/R13 = 13.7k each, R17 = 210k and R19 = 2.43k; R18 stays 10k. Current INA gain is 4.649635; post-HP gains are 22/108.419753, resistor-only totals 102.291971/504.112283. New ideal peak jack-to-ADC gains are 100.5408/495.4822. Start simulator-only sine tests at ≤ 12/2.4 mVpk open/closed under the stated offset/CM assumptions; these are not guaranteed ranges. At assumed 3.2 V and ±1.5 V usable swing, including 500 µV U4B Vos and two 0.5 mV follower allowances, downstream capacity/demand is 1.231/1.205. Fourth-order anti-alias filtering plus 8 kS/s gives more alias margin than sampling just above 1 kS/s. Driven reference senses common-mode rather than the differential signal. External isolation is respected as user choice but unverified.
Assumptions
One channel, standalone STM32F401 board, USB recording. The adopted gain split supports evaluating ±250 mV differential electrode DC offset as an assumed design-study envelope, not a confirmed performance requirement; also test ±100 mV independently of input common mode. Exact signal range/noise specification is not provided. Board size, final cable continuity map, isolator model, patient-current classification and qualification are unresolved. These are explicit prototype assumptions, not user-confirmed performance or safety guarantees.
Change Notes
2026-10-27 gain adoption, capture commit 063c2fe6: four resistor values changed as above; no topology, filter, protection or layout change, still 78 components and 49 nets. J2's stale protection wording was corrected to TPD2E2U06DRLR by the capture agent. That agent reports ERC 0 errors / 1 unchanged D4 pin-type warning. New ideal AC and headroom calculations are recorded in Gain Update Verification; total noise and RLD margins have NOT been re-established. AD8232 evaluation is separate; no substitution is adopted. Simulator bench only; no human-safety qualification.
2026-10-27: Surface-only clarification replaces needle-electrode requirement. User supplies external galvanically isolated USB power and data. Project renamed STM32 Surface EMG; initial architecture selected after read-only architecture review. User subsequently specified 0402 wherever possible and USB Type-C; these supersede the initial micro-B implementation suggestion. Electrical capture, independent review, focused power/interface corrections and ideal/simplified analog simulation are complete. 48 of 62 R/C components are 0402; larger exceptions and procurement gaps are documented. PCB drafting/placement/routing, firmware and hardware validation await the next phase.