The user authorized gain redistribution; capture commit 063c2fe6 applied it. This continuation independently read R12/R13/R17/R18/R19 and filter/ADC values with the schematic inspection tool, then ran new ideal AC and arithmetic checks. It edited project files ONLY. Counts of 78 components / 49 nets, no topology/filter/protection/layout change and fresh ERC 0 errors / 1 unchanged D4 unspecified-pin-type warning are the capture agent's report; this continuation did not rerun ERC. No AD8232 replacement was made.

U3/U4/J4/R18 gain notes and J2 stale USBLC6 wording were updated by capture. Actual D1 remains TPD2E2U06DRLR. Remaining 74 component values and all endpoints are in the updated Simulation Guide. Procurement MPNs/stock are not qualified. Optional tighter C23–C27 tolerances were not applied.

INA equation G1 = 1 + 100k/(R12 + R13) is the previously sourced manufacturer relation . Current G1 = 4.649635036496351. G2 = 1 + R17/R18 = 22 open; closed G2 = 1 + R17(1/R18 + 1/R19) = 108.41975308641976. Totals = 102.29197080291972 / 504.11228259890066, before loading. DC input attenuation a = 10M/(10M + 200k) = 1/1.02.

Independent magnitude calculation uses Hinput = 1/(1.02 + s·400k·52p), HHP = sR16C23/(1 + sR16C23), each HLP = 1/[1 + sCg(Ra + Rb) + s²RaRbCfCg], HADC = 1/(1 + s·100·1n), with s = j2πf and the guide's capacitor assignments. At 100 Hz this gives 98.5407359962 open vs SPICE 98.54068, difference ≈ 0.000057%. No guessed blanket 0.982 gain factor was used.

Both gain states, 1 Hz–1 MHz at 400 and 800 points/decade, with separate exact 20/100/500 Hz samples. Ideal unlimited INA/OPA and fixed VMID only; actual signal-path passives. No vendor model, finite bandwidth, saturation, supply drop, diode leakage/capacitance, RLD, noise or ADC switching. AC 1 V differential is normalization, not an operating amplitude.

LP2 internal passive-node peak is not itself amplifier clipping; follower input is LP2_B. Low-Q-first order is retained. Relative ideal filter shape remains the same because this ideal model changes constant gains only; real dynamics are not thereby validated.

Convergence 400 → 800 points/decade: open peak 100.5407 → 100.5408, closed peak 495.4819 → 495.4822; upper crossing 506.601 → 506.603 Hz. Requested spot gains change < 0.00084%; sampled peak frequency 254.0973 → 253.3670 Hz (0.29%), shallow peak. Exact-frequency samples avoid log-grid interpolation at 20/100/500 Hz. Stopband differences ≤ 0.0001 dB at displayed precision. Pass: numerical resolution; Warning: ideal-model omissions.

Evidence: 400-point run, 800-point run, exact-frequency run, structured fine sweep.

Each sine demand uses that amplifier's worst frequency over the sweep, not only 100 Hz. C23 removes settled INA DC downstream but not its startup/motion transient. Capacity/demand target is 1.2. All nominal passes are Warnings because rail, offset and active limits are assumed.

Reproduction: INA low test demand = G1·a·(0.250 + 0.012) = 1.194318019 V; at 0.100 + 0.012 V it is 0.510548161 V. Do not use the unloaded 1.218 V number for this input-stage demand. Internal A1out = VCM − G1·vd/2, A2out = VCM + G1·vd/2; vd is the loaded INA differential, and the ±vd/2 input contribution is included. Centered ideal jack DC + AC capacity = 1.5/(G1a) = 329.058085 mV before electronics/CM/corners.

U4D sine-only = 100.5408×0.012 = 1.2064896 V open and 495.4822×0.0024 = 1.18915728 V closed. Add 500 µV×G2 = 11.000/54.209877 mV and two 0.5 mV follower allowances: 1.2184896/1.244367157 V. Ratios 1.231032255/1.205432008 reproduce the prior review's rounded 1.231/1.205. No mandatory amplitude reduction follows from the nominal calculation; tolerance-qualified envelope is still unknown.

CM_SENSE nominal source Thevenin is 13.7k ∥ 13.7k = 6.85k, previously 2.495k. At assumed 60 pA U5A input current the static loading error is 0.411 µV. This is an ideal low-impedance-RG-node calculation, not vendor-validated dynamic input impedance.

With physical pin 1 RG1 paired to VIN−/A1 inverting input and pin 8 RG2 to VIN+/A2 inverting input, R12 pin 1 → midpoint and R13 midpoint → pin 8:

CMsense ≈ VCM + (vd/2)(R12 − R13)/(R12 + R13) + (R13Vos1 + R12Vos2)/(R12 + R13).

Equal halves give (Vos1 + Vos2)/2, with U5A Vos added downstream. Opposite ±0.1% errors still give mismatch magnitude 0.0005vd; sign follows R12 − R13. These are inverting-input nodes, not amplifier outputs.

Total revised noise/SNR/alias noise and RLD PM/GM were not computed or validated. Earlier detailed budgets and loop studies are historical. Gain redistribution changes actual INA noise gain, downstream noise amplification and RG loading; do not claim unchanged noise or loop margin. The 2.37× factor applies only to a constant INA output-referred term. Prior lumped 100 nV noise cannot identify a total penalty; U4B low-gain contribution alone scales approximately 4.88 → 11.6 µVrms ADC under historical assumptions.

Retain C30 10 nF pending loaded-loop/vendor/hardware evidence. Required next checks: full tolerance/active/rail/temperature corners; coupled supply/VMID startup; internal INA CM/offset fidelity; loaded RLD injection with real cable returns/mismatch, all crossings and GM; lead-open/reconnect/contact-short/clamp/motion recovery; full noise ownership/integration; actual ADC acquisition/reference/noise and calibrated simulator bench PSD/sine tests. Suggested targets remain headroom ≥ 1.2, PM ≥ 60° nominal / 45° corners, GM ≥ 6 dB, ADC error < 0.5 LSB and alias RMS ≤ 0.1× inband RMS; not medical standards. No Monte Carlo yield is claimed.

Bench electrode simulator only. Surface electrodes and J1 SJ-3524-SMT-TR remain tip 2 EMG+, ring 3 EMG−, sleeve 1 driven reference NEVER GND, switch 4 NC, no GPIO detector. External USB isolation, shield/SWD/instrument alternate grounds and fault/leakage qualification remain unknown; no human safety claim. Completed: current-state documents, live value readback, new ideal AC, convergence and independent/headroom arithmetic. Unattempted/blocked: vendor/nonlinear/full noise/current loop margins/hardware/safety. No Python, scripts or firmware deliverables.