USB-C Power Hub Design
Worked for 4 mins 49 sec
Assigned validated manufacturer names and MPNs to every requested capacitor, resistor, and L2 without changing connectivity or placement.
Open item
- The three “Missing Power” errors remain false positives: the STUSB control outputs are incorrectly typed as power inputs in their library symbols. The actual pull-up, NPN inverter, and eFuse-enable circuits are correct, and the available project editing controls cannot safely correct individual terminal types.
No new ERC errors were introduced.
Start Auto-Layout
Thought for 6 sec
I’ll inspect the board state and determine whether placement, routing, or both are required. I’ll apply the needed auto-layout steps, then verify airwires, overlaps, component containment, and DRC.
Worked for 11 mins 3 sec
PCB inspection completed:
- Current board is the default 160 × 100 mm, 4-layer layout.
- All 83 components are placed, but placement is scattered and partially routed.
- Both replacement and routing are needed; existing partial traces may become stale after replacement.
- Recommended direction: resize to approximately 50 × 80 mm or 80 × 80 mm, place the three USB-C receptacles at accessible edges, regroup the power/PD sections, then reroute and run DRC.
No layout changes were applied because available ACUs were exhausted during execution.
Configure 80mm board
Choose compact layout
Review PCB DRC
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Firmware Control Notes
MCU
STM32G071CBT6, 3.3 V, SWD on PA13/PA14 with NRST on PF2. Internal oscillator is assumed for first bring-up; external crystals are not populated.
Current Pin Map
Table
| MCU pin | Net / function | Notes |
|---|---|---|
| PA9 | I2C_SCL | Shared PD-controller control bus |
| PA10 | I2C_SDA | Shared PD-controller control bus |
| PA13 | SWDIO | Cortex debug header |
| PA14 | SWCLK / BOOT0 pin | Debug clock; boot option configuration must preserve SWD |
| PF2 | MCU_NRST | Header reset and 100 nF reset filter |
Controller Notes
- U1 STUSB4500: sink contract status, alerts, PDO/NVM configuration and VBUS path enable. Validate I2C address strapping and official register map.
- U2/U3 STUSB4710: source PDO selection and source enable. Their address straps must be made unique before firmware can share one I2C bus. The current first-pass schematic does not yet complete the address/PDO-select straps.
- U4/U5/U6 TPS25983: route PG, IMON and fault handling to spare ADC/GPIO in revision 2. Firmware must not rely only on PD controller state.
Required State Machine
- Boot on housekeeping rail with all downstream source paths disabled.
- Read/confirm upstream contract and cable-current capability.
- Compute available input power using the lower of negotiated contract, thermal derating, and measured-current ceiling.
- Keep Pi port priority. Advertise 5.1 V/5 A only when a compliant 5 A cable and sufficient budget are confirmed; otherwise cap at 3 A or deny.
- Advertise only display PDOs that fit remaining budget. Program converter setpoint before enabling its source path.
- On contract reduction, overcurrent, overtemperature or PG loss: withdraw display high-power PDOs, renegotiate, disable display if necessary, then reduce/disable Pi only if safety requires.
- Command VBUS discharge on detach/fault and verify VBUS-safe state before changing setpoint or reconnecting.
Register / Validation To-Do
- Import official STUSB4500 and STUSB4710 register maps and NVM/PDO programming procedure.
- Confirm STUSB4710 supports the desired dynamic PDO update workflow and USB PD 3.0 interoperability.
- Assign unique I2C addresses and interrupt GPIOs.
- Add ADC scaling constants for input, Pi and display current monitors after shunt/IMON networks are finalized.
- Define converter selector truth table or digital interface after the display power-stage redesign.
MCU
Current Pin Map
Controller Notes
Required State Machine
Register / Validation To-Do
