Temperature and Humidity Sensor Node Design

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Work completed
  • Decoupling capacitor C1: set to 100 nF, connected between U2 VCC and GND within 5 mm
  • Decoupling capacitor C2: set to 100 nF, connected between U2 AVCC and GND within 5 mm
  • Bulk capacitor C3: set to 10 µF, connected between U2 VCC and GND within 5 mm
  • Pull-up resistor R1: set to 10 kΩ, connected between U2 RESET and VCC
  • Protected 5 V entry circuit: oriented D1, TVS, and PTC with TVS breakdown > 5.25 V
  • Sabertooth headers: J2 Pin 1→U2 PD5, J3 Pin 1→U2 PD6; Pin 2 of each to GND
  • Encoder connectors: removed incorrect GND ties; J4 Pin 1→U2 PC4, Pin 3→U2 PC5, Pin 2→GND; J5 Pin 1→U2 PD2, Pin 3→U2 PD3, Pin 2→GND
  • AREF decoupling capacitor C4: 100 nF, connected between U2 AREF and GND within 5 mm
  • Pull-up resistors R2 and R3: each 10 kΩ, applied to ENC1_A and ENC1_B
  • ERC review passed with no errors and added to project property ERC_Review
  • Project properties set: Lock Net Names = true; Ground Pour Convention = “Pour ground on layers L2 and L3 with thermal spokes”; Initial Placement Approach = “Auto-Layout placement”
Success criteria review
  • ✅ All power, reset, and signal nets correctly connected with decoupling and bulk caps as specified
  • ✅ Sabertooth and encoder connectors properly mapped, no erroneous GND ties
  • ✅ ERC passed with no errors; schematic approved for PCB layout ground pour and placement
Next step Proceed to the PCB editor to apply ground pour on layers L2/L3 and run Auto-Layout placement of components.
91 days
certy

certy

why is J1 not connected
91 days

flux

1:48

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J1

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Short answer: J1 is the in-circuit programming header placeholder, but it hasn’t been wired to the ATmega’s ISP signals yet.
Details:
  • J1 is a 6-pin single-row header marked “ICSP,” but no nets are assigned to its pins in the schematic.
  • To make it functional, it must be connected to U2 as follows (AVR ISP 6-pin mapping):
    • Pin 1 → U2: PB4 (MISO)
    • Pin 2 → VCC
    • Pin 3 → U2: PB5 (SCK)
    • Pin 4 → U2: PB3 (MOSI)
    • Pin 5 → U2: RESET/PC6 (and keep R1 10 kΩ pull-up to VCC)
    • Pin 6 → GND
Optionally, we can swap J1 to the standard keyed 2x3 AVR ISP footprint for tooling compatibility: 2x3 Pin Header.
Want me to wire J1 per the mapping above and, if you prefer, replace it with a keyed 2x3 header?
Header wiring help
Search keyed ISP header
Replace J1 footprint
Confirm mapping nets
91 days

Plan completed.

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U1 PC6_(~RESET~/PCINT14) - R1 P1
R2
Resistance
10k Ω
D1 K - PTC P2
C4
Capacitance
Capacitance
TVS 3 - TVS 4
U1 PC6_(~RESET~/PCINT14) - R1 P1
J3 1 - U2 PD6
C3
Capacitance
10uF
R2
Resistance
500 Ω
R2 P2 - R3 P2
D1 K - PTC P2
D1 A - PTC P1
C1
Capacitance
100nF
U2 PD3 - J5 Pin_3
C3 P2 - GND GND
U2 PD3 - J5 Pin_3
C2
Capacitance
100nF
C3 P2 - GND GND
U1 PD2_(INT0/PCINT18) - J5 Pin_1
D1 A - PTC P1
TVS 3 - TVS 4
D1 K - PTC P2
J2 1 - U2 PD5
U1 GND_1 - C1 P2
D1 K - PTC P2
C3 P2 - GND GND
R2 P2 - R3 P2
C3 P2 - GND GND
U1 (PCINT19/OC2B/INT1)_PD3 - J5 Pin_3
U1 PC5_(ADC5/SCL/PCINT13) - J4 Pin_3
U1 PD2_(INT0/PCINT18) - J5 Pin_1
C3 P2 - GND GND
U2 PD2 - J5 Pin_1
R3
Resistance
10k Ω
C3 P2 - GND GND
U1 PC4_(ADC4/SDA/PCINT12) - J4 Pin_1
U2 PD2 - J5 Pin_1
U1 PC5_(ADC5/SCL/PCINT13) - J4 Pin_3
R1
Resistance
10k Ω
GND
J5
TVS
D1
PTC
J2
J3
J4
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Relative Harlequin Robot Vacuum

Relative Harlequin Robot Vacuum
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Last updated by certy
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certy

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