Phase A Design Review
Worked for 1 min 8 sec
The live board is already configured as 140 × 85 mm, six layers, so I will not repeat setup. Gate C has exposed two concrete issues to resolve: the present one-sided footprint area is critically dense, and 60 generic passives still lack manufacturing MPNs; I’m now auditing the critical connector/IC footprints and pin maps before deciding whether the outline can remain fixed.
Worked for 6 mins 57 sec
Critical verification found three real layout blockers: U6 has an incorrect library pin map, T1 has incorrect center-tap/NC semantics, and L1’s 6.8 µH/8 A assignment is physically impossible in 0603. I’m correcting those three with inspected datasheet-backed parts, then I’ll finish the remaining discrete-footprint audit and recheck the gate.
Thought for 22 sec
Gate C verification advanced without repeating completed work. The 140 × 85 mm six-layer setup was confirmed, and critical IC/connector footprints were audited.
- Verified: U1–U5, U8, U10, J2, and J3.
- Corrected metadata: U6 package/datasheet, U8 datasheet, and K1 MPN.
- Blockers found: incorrect U6 pin map, incorrect T1 center-tap/NC mapping, and L1’s impossible 6.8 µH/8 A 0603 package.
- Provisional: U9 exposed-pad variant, K1 output-pin mapping, J1 orientation/edge datum, and J4–J8 interface intent.
- Remaining: repair U6/T1, select a qualified L1, audit remaining discrete footprints, rerun ERC/physical checks, then begin placement.
Work stopped because no ACUs are currently available.
Fix Gate C blockers
Select L1 replacement
Audit discretes
Clarify J4–J8
Check after fixes
Refine this doc
Ask about this doc
Phase A Design Notes
Decision Summary
- Source of truth: uploaded clean-sheet specification only; no prior design files used.
- Architecture: protected 28 V entry -> 5.2 V synchronous buck -> external switch and secondary 3.3 V buck; isolated logic hold-up branch; RMII PHY plus magnetics; self-powered USB-UART; fail-safe external I/O; floating TLP3547 contact.
- Recommended stackup: 6 layers.
- Provisional board size: 140 mm x 85 mm, center datum, four M3 holes 5 mm from corners.
- Fabrication release is explicitly blocked by the Section 17 confirmations.
Hold-up First-Pass Calculation
Assume the backed-up load is limited to ESP32, brownout status, and minimum safe-state logic at 250 mA average on 3.3 V for 100 ms. Required energy is approximately:
E = V x I x t = 3.3 x 0.25 x 0.1 = 0.0825 J.
For a capacitor discharged from 5.0 V to 3.6 V through a buck-boost stage at 85% efficiency:
C = 2E / (eta x (V1^2 - V2^2)) = 0.019 F approximately.
A nominal 47 mF to 100 mF storage element provides useful derating and transient margin if the backed-up load is tightly isolated. If the full 700 mA 3.3 V peak must be sustained, required nominal storage rises toward 0.1 F. Final capacitance must include ESR, tolerance, temperature, converter UVLO, charger current, and actual load measurements.
3.3 V Regulator Thermal Rationale
An LDO from 5.2 V to 3.3 V at the provisional 700 mA peak would dissipate:
P = (5.2 - 3.3) x 0.7 = 1.33 W.
This is excessive for a compact low-noise LDO without a large thermal package and copper area, so a synchronous buck is the baseline.
Input Current First Pass
At 5.2 V and 3.9 A peak, output power is 20.3 W. At 18 V input and 90% efficiency, converter input current is about 1.25 A. This excludes the protected Tic motor branch. The final fuse, reverse-protection FET, D-Sub contact current, and input copper must therefore be selected only after the motor load and source transient profile are confirmed.
Stackup Comparison
Table
| Attribute | 4 layer | 6 layer |
|---|---|---|
| Cost | Lower | Higher |
| Top high-speed reference | Excellent with L2 GND | Excellent with L2 GND |
| Bottom high-speed reference | Poor if L3 is fragmented power | Excellent with L5 GND |
| Routing capacity | Marginal for five Ethernet paths, RMII, USB, power, motor | Strong |
| Power partitioning | Competes with signal routing | Dedicated plane plus inner signal layer |
| EMC risk | Higher | Lower |
| Recommendation | Feasible only after detailed placement proves continuous returns | Preferred baseline |
Major Risks to Carry into Phase B
- The 50 MHz clock-output mode on ESP32 GPIO17 must be verified against current ESP-IDF Ethernet support and LAN8720A timing.
- TLP3547 suffix, package, and contact ratings must be verified against the actual HD80 button circuit.
- Exact D-Sub and internal connector footprints cannot be finalized without mating and mechanical confirmation.
- TVS, fuse, reverse-polarity, EMI damping, and motor copper are provisional until the input and motor environments are known.
- Camera/limit/encoder interface population must remain configurable or DNP until voltage standards are confirmed.
Decision Summary
Hold-up First-Pass Calculation
3.3 V Regulator Thermal Rationale
Input Current First Pass
Stackup Comparison
Major Risks to Carry into Phase B
