• Status: Draft - Phase A architecture complete; fabrication release blocked by unresolved interface and environmental assumptions.
• Goal: Clean-sheet 28 V controller PCB using ESP32-WROOM-32UE-N16, wired 10/100 Ethernet, USB-UART programming, external five-port switch interfaces, Pololu Tic 36v4 control, protected low-speed I/O, camera enable, HD80 virtual-button PhotoMOS relay, brownout monitoring, and logic-only ride-through.
• The uploaded specification is the source of truth. No prior project files are required or used.

• Accept nominal 28 VDC through a fixed 44-pin D-Sub interface.
• Generate V5P2 for the external Ethernet switch and V3P3 for controller logic.
• Run an ESP32-WROOM-32UE-N16 with production Wi-Fi/Bluetooth disabled.
• Connect the ESP32 MAC to a 10/100 PHY over RMII and isolated Ethernet magnetics.
• Route four additional switch Ethernet ports between internal keyed connectors and the D-Sub.
• Provide self-powered USB-to-UART programming, VBUS sensing, ESD protection, and automatic boot/reset.
• Interface a Pololu Tic 36v4 module, limit inputs, encoder/serial lines, camera detect/enable, brownout monitor, and an isolated HD80 button-contact emulator.
• Preserve essential logic briefly after loss of 28 V without backing up switch, motor, or camera payload power.

• 18-32 V provisional operating range with fuse, reverse protection, surge clamp, EMI filter, and protected Tic branch.
• Five keyed Ethernet port connectors plus one duplicated-contact switch power connector.
• USB 2.0 full-speed D+/D- through the D-Sub, with upstream VBUS only on pin 33.
• TLP3547 normally-open polarity-independent floating contact.
• Four M3 mounting holes, external antenna access, test points, and controlled-impedance routing.

Diagram

1. D-Sub and external I/O.
2. Input protection and power conversion.
3. External switch ports and switch power.
4. USB-UART and automatic programming.
5. Tic 36v4 and protected low-speed I/O.
6. RMII PHY, magnetics, and local switch port.
7. ESP32 controller, boot/reset, decoupling, and test access.
8. Camera-enable options and HD80 PhotoMOS relay.

• Main external connector pinout is fixed exactly as provided in the uploaded specification.
• Ethernet pair names remain polarity-preserving and will be documented by endpoint perspective.
• USB_VBUS is a host-sense input and must never be tied directly to V5P2.
• HD80_BUTTON_A/B remain floating from all board rails and ground.
• Camera enable is a control signal, not payload power.

• Input: 18-32 VDC provisional, nominal 28 V.
• V5P2: design target at least 3 A continuous; recommended converter capability 5 A to preserve switch-load and logic margin.
• V3P3: design target at least 1 A continuous with transient margin.
• Logic hold-up: provisional 100 ms for ESP32 plus only essential monitoring/control loads.

• Provisional outline: 140 mm x 85 mm rectangular board, datum at board center, four M3 holes 5 mm from corners. This is deliberately independent of any prior design.
• D-Sub and harness connectors occupy board edges; antenna connector/cable access receives a mechanical and copper keepout.
• Provisional stackup: 6 layers recommended: L1 signal/components, L2 solid GND, L3 signal, L4 power, L5 solid GND, L6 signal/components. A 4-layer board is technically possible but would constrain bottom-layer high-speed return paths and power partitioning across the large connector/power/motor design. Six layers reduce routing and EMC risk enough to justify the cost.
• Controlled-impedance geometries remain provisional until the fabricator provides a released stackup.

• Production-intent assembly with verified MPNs, footprints, 3D bodies, exposed-pad paste, connector mating envelopes, and M3 hardware.
• Exact fabricator and capabilities are not yet selected.
• No fabrication-ready claim is allowed while mandatory assumptions remain unresolved.

• Use a clean-sheet architecture and independent board outline.
• Use a 5 A-class 60 V buck baseline rather than sizing exactly to the 3 A minimum.
• Use a switching 3.3 V regulator rather than an LDO to avoid approximately 1.3 W worst-case dissipation at 700 mA.
• Use a six-layer stackup provisionally because the design combines USB, RMII, five Ethernet-port paths, motor current, and noisy 28 V conversion.
• Back up only ESP32 and essential monitor/control logic. Switch, Tic motor stage, and camera payload are excluded.

1. 28 V source: 18-32 V steady-state; surge profile, source impedance, reverse polarity, grounding, current, and environmental standard unknown.
2. Switch: 3.0 A maximum at 5.2 V provisional; actual load and cable drop unknown.
3. Tic motor: current, motor inductance, duty cycle, header geometry, motor mapping, and harness rating unknown.
4. Hold-up: 100 ms target; essential backed-up load and acceptable droop not confirmed.
5. D-Sub: exact part, shell, mating view, mounting, current rating, pin-33 VBUS availability, and chassis treatment unknown.
6. Board mechanics: final outline, mounting coordinates, height, edge locations, enclosure, airflow, and antenna cable route unknown.
7. Switch connectors: family, pair perspective/crossover, shielding, and cable lengths unknown.
8. Camera detect/enable: voltage, polarity, current, pulls, unpowered behavior, cable environment, isolation need, and output mode unknown.
9. HD80 button: open-circuit voltage, closure current, floating/reference status, pulse duration, debounce, connector, cable, and faults unknown.
10. Limit/encoder lines: electrical levels, polarity, bandwidth, cable length, noise, and debounce/filtering unknown.
11. Fabricator: stackup, copper weight, impedance tolerance, materials, temperature range, coating, cleaning, and test requirements unknown.

• Every required functional block is assigned to an architecture block.
• Every fixed D-Sub pin is assigned by the uploaded specification and will be captured without reinterpretation.
• The GPIO map has no unresolved boot-strap conflict under the stated fail-safe bias requirements.
• Major components and alternates are identified provisionally.
• Power budget exposes the switch and motor-load uncertainty rather than hiding it.
• Six layers and a provisional 140 mm x 85 mm outline are selected for continued design.
• Gate A status: PASS for provisional schematic capture; fabrication release remains BLOCKED.

• Initial Phase A specification created from the uploaded clean-sheet requirements.