Phase A Design Review
Worked for 1 min 8 sec
The live board is already configured as 140 × 85 mm, six layers, so I will not repeat setup. Gate C has exposed two concrete issues to resolve: the present one-sided footprint area is critically dense, and 60 generic passives still lack manufacturing MPNs; I’m now auditing the critical connector/IC footprints and pin maps before deciding whether the outline can remain fixed.
Worked for 6 mins 57 sec
Critical verification found three real layout blockers: U6 has an incorrect library pin map, T1 has incorrect center-tap/NC semantics, and L1’s 6.8 µH/8 A assignment is physically impossible in 0603. I’m correcting those three with inspected datasheet-backed parts, then I’ll finish the remaining discrete-footprint audit and recheck the gate.
Thought for 22 sec
Gate C verification advanced without repeating completed work. The 140 × 85 mm six-layer setup was confirmed, and critical IC/connector footprints were audited.
- Verified: U1–U5, U8, U10, J2, and J3.
- Corrected metadata: U6 package/datasheet, U8 datasheet, and K1 MPN.
- Blockers found: incorrect U6 pin map, incorrect T1 center-tap/NC mapping, and L1’s impossible 6.8 µH/8 A 0603 package.
- Provisional: U9 exposed-pad variant, K1 output-pin mapping, J1 orientation/edge datum, and J4–J8 interface intent.
- Remaining: repair U6/T1, select a qualified L1, audit remaining discrete footprints, rerun ERC/physical checks, then begin placement.
Work stopped because no ACUs are currently available.
Fix Gate C blockers
Select L1 replacement
Audit discretes
Clarify J4–J8
Check after fixes
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Gate B Design Calculations
Power Budget
- V5P2 external switch: 2.0 A typical / 3.0 A peak.
- V3P3: 252 mA typical / 700 mA peak. Reflected to V5P2 at 90%: 0.178 A typical / 0.493 A peak.
- Miscellaneous V5P2 allowance: 0.10 A typical / 0.20 A peak.
- Reconciled V5P2 total: approximately 2.28 A typical / 3.69 A peak (the prior 3.90 A figure remains a conservative rounded design ceiling).
- At 18 V and 90% LM76005 efficiency, 5.2 V × 3.9 A reflects 1.25 A input. Tic motor current is excluded and remains a release blocker. A 0.5 A 1812 PTC is not acceptable as the final common input fuse for this budget.
Logic Hold-up
Implemented scope is ESP32 plus essential safe-state monitoring/control only on
V3P3_ESS; Ethernet PHY, USB-UART, translated Tic/payload branch, camera payload power, and the external V5P2 branch remain on non-backed rails. Worst-case backed load is 250 mA at 3.3 V for 100 ms (0.0825 J). Storage is C30+C11 = 94 mF nominal at HOLDUP_STORE. TPS2121RUXR U10 performs automatic highest-voltage selection, 5 us fast switchover, always-on reverse-current blocking, and a nominal 1.5 A output limit (R40=80.0 kΩ). TPS62130ARGTR U11 converts the muxed 5.2 V domain to 3.328 V nominal on V3P3_ESS.C = 2×0.0825 / [0.85×(5.0²−3.6²)] = 16.2 mF ideal.Including -20% initial tolerance, -15% aging, -10% cold-temperature capacitance, 0.20 V ESR/transient allowance, 0.5 mA storage leakage, and 0.8 mA combined mux/buck operating overhead gives a required nominal range of approximately 72-86 mF; 94 mF was selected. At 5.0 V initial storage and 3.6 V converter-input endpoint, available derated energy exceeds 0.10 J at 85% conversion efficiency, meeting 100 ms at 250 mA with margin. This is not sized for a sustained 700 mA whole-V3P3 event; nonessential loads are explicitly excluded.
Charging is V5P2 -> R38 51 Ω/1 W -> D4 SS56 -> storage. Initial charge is about (5.2-0.3)/51 = 96 mA, below the prior 100 mA target; RC tau is 4.79 s, about 14.4 s to 95% and 22.1 s to 99%. D4 blocks storage backfeed to V5P2 and all external interfaces. R39=10 kΩ provides controlled discharge (nominal tau 940 s). U10 automatically returns to IN1 when V5P2 is restored; U11 soft-start is set by C34=3.3 nF. U10 IQ is 300 µA typical/400 µA max, standby-input current 15 µA typical/25 µA max, reverse leakage up to 500 µA over temperature, and fast RCB response is 10 µs. U11 IQ is 17 µA typical/30 µA max. R38 sees about 0.47 W initially and is rated 1 W; energy during a full recharge is below its pulse capability subject to layout thermal verification. U10 and U11 have thermal shutdown; U11 peak load is far below its 3 A rating and L4 is rated 3.8 A.
Alternatives rejected: a single resistor/diode directly ORed onto V3P3 cannot isolate the Tic/payload branch or guarantee switchover; a 5.5 V 0.1 F memory supercapacitor found in-library has 25 Ω ESR and fails the transient droop requirement; a TPS22946 charger times out after 10 ms of current limit and is unsuitable for a 94 mF bank. The selected separate limited charger + TPS2121 mux + dedicated buck wins on explicit load isolation, deterministic reverse blocking, fault containment, and seamless restoration.
TLV6700 Brownout Window
TLV6700 reference is nominally 0.4 V. Implemented dividers:
- Undervoltage: 432 kΩ / 10 kΩ => nominal threshold 17.68 V.
- Overvoltage: 787 kΩ / 10 kΩ => nominal threshold 31.88 V.
- OUTA and OUTB are open-drain wired together as
BROWNOUT_N, pulled to V3P3 by 10 kΩ. - 100 nF VDD decoupling and 10 nF UV input filtering are captured.
Worst-case thresholds must include the TLV6700 reference limits plus 1% resistor ratio error; external hysteresis was not added because its polarity and magnitude must be reviewed against the exact Rev. B equations.
BROWNOUT_N is safe when the 28 V domain is absent because the outputs are open-drain and the input-divider current flows only into the comparator input network; final leakage/back-power validation remains required.Regulator Support Captured
- LM76005: 6.8 µH, 470 nF BOOT-to-SW, 2.2 µF VCC, 22 nF SS (~11 ms), 100 kΩ-class feedback network, nominal 200 µF output bank, protected-VIN ceramic input. The nominal 5.2 V divider is 105 kΩ / 24.9 kΩ (5.22 V).
- TPS62130A: 2.2 µH, 10 µF input, 22 µF output, 100 nF AVIN bypass, 3.3 nF SS, PG open-drain network already present.
- Effective MLCC capacitance, RMS ripple, exact inductor MPN/DCR/Isat, and thermal derating remain BOM-release checks.
Fabrication-release blockers
- Tic motor current/duty and harness/contact rating; therefore final common fuse/PTC/current-limit value is unresolved.
- Surge standard/source impedance; SMBJ33A clamps to about 53.3 V at rated pulse and must be coordinated with the LM76005/LTC4368/MOSFET SOA.
- Logic hold-up is electrically captured; fabrication verification remains measured backed-load current, capacitor ESR/tolerance at temperature, and 100 ms removal/restoration bench test.
- Camera voltage/polarity/current/unpowered behavior/cable environment; configurable push-pull vs DNP open-drain population remains required.
- HD80 real open-circuit voltage, closure current, closure duration, cable faults, and mating connector. Firmware momentary duration is configurable; hardware must default off during reset/boot.
- Chassis/shield bonding and external cable shield strategy.
- Controlled-impedance stackup release and connector mating/mechanical data.
Live Completion Pass — 2026-08-04
- Fresh pre-mutation ERC baseline was 41 errors, all floating-pin findings.
- Removed twelve electrically floating, unassigned placeholder passives (R12–R16, R38–R40, C11–C12, C30–C31) rather than inventing connections.
- Connected C21–C24 as 100 nF/16 V 0603 V3P3 decouplers and connected every verified duplicate ESP32 GND terminal plus TPS62130A PGND pin 15 to GND.
- HD80 input drive now uses R22 = 390 ohm, 1%, 0.1 W, Yageo RC0603FR-07390RL, giving approximately (3.3 V − 1.3 V)/390 ohm = 5.1 mA nominal. R23 is 100 kohm, 1%, Yageo RC0603FR-07100KL for reset/boot default-off gate bias. The floating NO contact remains isolated on J3.
- Fresh post-mutation ERC: 0 unresolved errors and 0 ERC warnings at 2026-08-04T04:46:35Z.
- Logic hold-up is now electrically complete: U10 TPS2121RUXR, U11 TPS62130ARGTR, C30+C11 94 mF storage, R38/D4 limited reverse-blocked charger, R39 bleed, L4 and complete regulator support, plus TP17. Gate B is electrically complete but not fabrication-released pending camera/HD80 field data and hold-up bench correlation.
- Unknown HD80 field voltage/current/pulse duration and camera electrical behavior remain release blockers; ERC cleanliness does not qualify these interfaces for fabrication.
Power Budget
Logic Hold-up
TLV6700 Brownout Window
Regulator Support Captured
Fabrication-release blockers
Live Completion Pass — 2026-08-04
