Schematic Completion Report
Scope status
- Completed: Datasheet/symbol preflight for J1, U4, U5, and U2/U3; all safe power, level-shifter, display, header, net-name, passive-addition, and placement work.
- Blocked: Full U2/U3 wiring because the installed
TPIC6B595DWR symbol pin numbering does not match TI SLIS032D.
- Unattempted by instruction: Routing of the remaining board airwires. Only the existing J2/J3 pin-6 bus copper was reassigned from GND to RCK using the same straight geometry.
Datasheet and symbol preflight
The immutable citation pipeline was still indexing these PDFs, so the facts below were checked from OCR-extracted manufacturer PDF content but do not have inline immutable citations.
U2/U3 — TPIC6B595DWR
TI SLIS032D DW/N pinout expects:
- GND: pins 10, 11, 19
- RCK: pin 12
- SRCK: pin 13
- DRAIN4–DRAIN7: pins 14–17
- SER OUT: pin 18
Installed U2/U3 symbols contain:
- GND: pins 10, 18, 19
- RCK: pin 12
- SRCK: pin 11
- DRAIN4–DRAIN7: pins 13–16
- SER OUT: pin 17
Therefore pins 11 and 13–18 are mislabeled. Per the specification, those affected symbol pins were not newly wired. Safe matching pins 2–10, 12, 19, 1, and 20 were used as applicable.
Functional consequences:
- Each driver’s actual GND pin 11 remains unconnected because the symbol calls it SRCK.
- Each driver’s SRCK pin 13 remains unconnected because the symbol calls it DRAIN4.
- DRAIN4–DRAIN7 cannot be safely connected to the segment resistors.
- The existing
SER_CASCADE connection is preserved and renamed, but the symbol connects U3 pin 17 to U2 SER IN. On the real IC pin 17 is DRAIN7, not SER OUT. Actual SER OUT is pin 18, which the symbol calls GND. Thus the cascade is not physically correct until the part symbol is repaired.
J1 — Tensility 54-00164
Manufacturer drawing mapping read from the PDF:
- A1 and A2: outer sleeve contact
- B: center/tip contact
- C: switched contact
Wiring completed: B → +12V; A1/A2 → GND; C intentionally no-connect.
U4 — LM1117IMPX-5.0/NOPB
Verified fixed-voltage SOT-223 mapping: pin 1 GND, pin 3 VIN, pins 2 and 4/tab VOUT. The datasheet requires at least 10 uF output capacitance and specifies output-capacitor ESR of 0.3–22 ohms.
U5 — SN74AHCT125DR
Verified SOIC-14 mapping matches the project symbol: 1OE/1A/1Y = 1/2/3; 2OE/2A/2Y = 4/5/6; GND = 7; 3Y/3A/3OE = 8/9/10; 4Y/4A/4OE = 11/12/13; VCC = 14. Unused CMOS inputs must be held at VCC or GND.
Completed connectivity
Power
- J1 B → +12V; J1 A1/A2 → GND.
- U4 VI → +12V; GND → GND; VO pin 2 and tab pin 4 → +5V.
- C1 100 nF/25 V and C2 10 uF/25 V from U4 VI to GND.
- C3 10 uF/10 V tantalum from U4 VO to GND; role details record the required 0.3–22 ohm ESR range.
- C4 100 uF/25 V bulk from +12V to GND near J1.
- U1 VSYS → +5V; all eight named GND pins and AGND → GND.
- DS1 and DS2 CA1/CA2 → +12V.
Level shifting
- U5 pin 14 → +5V with C5 100 nF to GND; pin 7 → GND.
- All four active-low OE pins → GND; 4A → GND; unused 4Y marked no-connect.
- U1 GPIO19 → 1A; GPIO18 → 2A; GPIO17 → 3A.
- 1Y → R17 33 ohm 0805 → DATA.
- 2Y → R18 33 ohm 0805 → SRCK.
- 3Y → R19 33 ohm 0805 → RCK.
Drivers — safe pins only
For both U2/U3:
- VCC pin 2 → +5V with local C6/C7 100 nF decoupling.
- Verified GND pins 10 and 19 → GND.
- Active-low G pin 9 → GND.
- RCK pin 12 → RCK.
- Active-low SRCLR pin 8 shared on
SRCLR_N, pulled to +5V by R20 10 kOhm.
- DATA → U3 SER IN pin 3.
- Existing U3 SER OUT-symbol → U2 SER IN connection renamed
SER_CASCADE; electrically blocked by the symbol error described above.
- DRAIN0–DRAIN3 connected to R1–R4 and R9–R12 using the inspected free resistor terminals.
Blocked drain connections:
- U2 DRAIN4–7 → R5–R8.
- U3 DRAIN4–7 → R13–R16; R16 free terminal P1 confirmed.
Display/header nets
- J2/J3 pin 2 remains GND.
- J2/J3 pin 6 is RCK.
- The old pin-6 GND trace was removed and recreated on RCK with the same straight bottom-layer geometry and 1 mm width. No dangling trace remains.
- Segment nets are named
DS1_A … DS1_G, DS1_DP, and DS2_A … DS2_G, DS2_DP; the previously missing DS2 D connection was created as DS2_D.
Net 16 renamed SER_CASCADE.
New passives and placement
Added R17–R20 and C1–C7 with required Role/Role Details. R17–R19 are 33 ohm SMD_0805_2012Metric. All new parts are on the bottom, in bounds, and have zero new overlaps or keepout violations.
Configured package properties:
- C1/C5/C6/C7:
SMD_0805_2012Metric
- C2/C3:
SMD_1206_3216Metric
- C4:
CP_Elec_8x10
Layout uncertainty: the layout summary currently renders every new generic capacitor with an approximately 0805-sized 2.45 × 1.02 mm body despite the larger configured package properties for C2/C3/C4. No missing-footprint check is reported, but the physical package regeneration appears stale or unsupported and must be confirmed before fabrication.
Remaining unconnected pins on requested components
Intentional unused / no-connect
- U1: 3V3, 3V3_EN, ADC_VREF, GPIO0–GPIO16, GPIO20–GPIO22, GPIO26_ADC0, GPIO27_ADC1, GPIO28_ADC2, RUN, SWCLK, SWDIO, TP1–TP6, VBUS. These are marked no-connect. The ERC power-pin checker still reports VBUS as missing power despite the intentional no-connect.
- U2: NC pins 1 and 20 marked no-connect.
- U3: NC pins 1 and 20 marked no-connect.
- U5: 4Y marked no-connect; 4A and 4OE are held at GND.
- J1: switched contact C marked no-connect.
Blocked errors from the TPIC symbol mismatch
- U2: SRCK(symbol pin 11 / actual GND), DRAIN4(symbol 13 / actual SRCK), DRAIN5(symbol 14 / actual DRAIN4), DRAIN6(symbol 15 / actual DRAIN5), DRAIN7(symbol 16 / actual DRAIN6), SER OUT(symbol 17 / actual DRAIN7), GND(symbol 18 / actual SER OUT).
- U3: SRCK(symbol pin 11 / actual GND), DRAIN4(symbol 13 / actual SRCK), DRAIN5(symbol 14 / actual DRAIN4), DRAIN6(symbol 15 / actual DRAIN5), DRAIN7(symbol 16 / actual DRAIN6), GND(symbol 18 / actual SER OUT). The symbol’s SER OUT pin 17 is already on
SER_CASCADE, but physically that pad is DRAIN7.
- Corresponding resistor free terminals remain floating: R5:P2, R6:P2, R7:P2, R8:P2, R13:P2, R14:P2, R15:P2, R16:P1.
No remaining unconnected pins
- U4: none.
- DS1: none.
- DS2: none.
- J2: none.
- J3: none.
Decoupling audit
Requested decoupling/support is present for U4, U5, U2, and U3. No requested rail or safe IC power pin is missing a capacitor. The unresolved U2/U3 actual pin-11 ground connections are symbol blockers, not missing capacitors.
Verification evidence
- Final netlist inspected after mutation and contains all completed rails, series paths, segment names, RCK, SRCLR_N, and SER_CASCADE.
- ERC reports 21 floating pins, all traceable to the TPIC symbol mismatch and the eight blocked drain-resistor terminals.
- ERC additionally reports U1 VBUS missing power despite intentional no-connect.
- DRC reports 59 remaining airwires, intentionally not routed per scope; 0 dangling traces.
- New passive placement: 0 overlaps introduced, 0 keepout violations, 0 out-of-bounds.
- One pre-existing placement warning remains: DS1 overlaps J3 on Top by 14.39 mm²; it was not modified because the specification prohibited disturbing fixed display/header geometry.
- The rigorous schematic-review tool returned no matched items because of a tool filtering failure; direct final netlist inspection and ERC/DRC checks were used instead.