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Functional Verification Report

Review date: 2026-09-01
Scope: Read-only review of the current schematic and PCB. No fixes were applied.
Evidence policy: PASS means confirmed from live project data and, where required, immutable datasheet evidence. FAIL means live project data demonstrates a functional or manufacturing defect. UNVERIFIED means the required external evidence or physical mapping was unavailable. Datasheet indexing returned “immutable evidence not ready” for the TPIC6B595 and SN74AHCT125 queries, so claims requiring datasheet clauses are not promoted to PASS.

Executive result

Overall: FAIL. The schematic signal topology is coherent, but the board has active PCB errors and the 12 V-to-5 V linear-regulator architecture has a severe thermal ri...

flux

Completed the read-only functional review in Functional Verification Report.

Overall: FAIL. Primary blockers are J1/J3/DS1 placement and copper conflicts, LM1117 thermal dissipation, unsafe/unverified USB–12 V power interaction, and the unverified 40101B-5 pinout. No design changes were applied.

brianbenchoff

tell me what this board is supposed to do and how you accomplished it, new document in the files

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Created a project doc

Purpose and Implementation

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Purpose and Implementation What This Board Is Supposed to Do

The Days Since Counter is a large, network-capable two-digit counter intended to show the number of days since a selected event. Typical uses include “days since the last incident,” “days since a milestone,” or any other value that can be represented from 00 to 99.

The Raspberry Pi Pico 2 W provides the intelligence and wireless connectivity. Firmware determines the value to display—either by calculating elapsed days from a stored date or by receiving an updated value over Wi-Fi—and converts the two decimal digits into seven-segment patterns.

The board is designed as a self-contained sign:

A 12 V DC input powers the board.
Two large common-anode seven-segment modules provide the visible digits.

flux

Created Purpose and Implementation. It explains the board’s intended “days since” function, power architecture, Pico firmware role, logic buffering, serial display drivers, LED current paths, expansion bus, and physical PCB implementation.

Files

Schematic

Layout

3D View

DS1

DS2

R12

Resistance

220 ohms

R13

Resistance

220 ohms

Capacitance

100nF

R11

Resistance

220 ohms

R20

Resistance

10kOhms Ω

Flux Logo1

Resistance

220 ohms

R19

Resistance

33ohms Ω

Capacitance

100uF

Resistance

220 ohms

Resistance

220 ohms

Resistance

220 ohms

Resistance

220 ohms

R15

Resistance

220 ohms

R16

Resistance

1000 ohms

Resistance

1000 ohms

R18

Resistance

33ohms Ω

Capacitance

100nF

Resistance

220 ohms

Capacitance

100nF

Capacitance

10uF

R17

Resistance

33ohms Ω

R10

Resistance

220 ohms

R14

Resistance

220 ohms

Capacitance

100nF

Resistance

220 ohms

Capacitance

10uF

Resistance

220 ohms

Functional Verification Report

Executive result

Overall: FAIL. The schematic signal topology is coherent, but the board has active PCB errors and the 12 V-to-5 V linear-regulator architecture has a severe thermal risk for a Wi-Fi-enabled Pico load. USB-only and dual-source behavior is also not safely established.

1. Pin-map provenance

Table

Item	Result	Evidence / consequence
U1 Raspberry Pi Pico 2 W symbol numbering	UNVERIFIED	Live symbol maps GPIO17/18/19 to physical pins 22/24/25, VSYS to 39, VBUS to 40, and grounds to the expected module positions. Required immutable manufacturer citation and symbol-to-footprint pad inspection were not available in this pass.
U2/U3 TPIC6B595 pin names and numbers	UNVERIFIED	Live symbol is: NC 1, VCC 2, SER IN 3, DRAIN0–3 4–7, /SRCLR 8, /G 9, GND 10/11, RCK 12, SRCK 13, DRAIN4–7 14–17, SER OUT 18, GND 19, NC 20. This is internally consistent, but the requested immutable datasheet clause and footprint-pad proof were unavailable because indexing was not ready. A wrong pad map would cross-connect logic, drains, or power.
U4 LM1117 pin names and numbers	UNVERIFIED	Live symbol maps GND=1, VO=2 and tab/pad 4, VI=3. Footprint-pad geometry and immutable datasheet clause were not retrieved.
U5 SN74AHCT125 pin names and numbers	UNVERIFIED	Live symbol uses standard quad-buffer order: /1OE 1, 1A 2, 1Y 3; /2OE 4, 2A 5, 2Y 6; GND 7; 3Y 8, 3A 9, /3OE 10; 4Y 11, 4A 12, /4OE 13, VCC 14. Datasheet evidence and footprint-pad proof were unavailable.
DS1/DS2 40101B-5 mapping	UNVERIFIED	The project part explicitly states that its geometry is user-controlled and that no external compatibility or datasheet claim is made. Current assignment is CA1=1, E=2, D=3, C=4, DP=5, B=6, A=7, CA2=8, F=9, G=10. No manufacturer source confirming CA1=1 / CA2=8 was found. If CA pins are wrong, +12 V may be applied to a segment pin while a common-anode pin is driven through a resistor/TPIC drain, causing incorrect display behavior and possible component overstress.
J1 Tensility 54-00164 pin/pad mapping	UNVERIFIED	Live nets use B=+12 V and A1/A2=GND; C is unused. The exact manufacturer contact-function and footprint-pad mapping was not established with immutable evidence.

2. DATA, SRCK, RCK, and cascade

Live signal paths

DATA: U1 GPIO19 (pin 25) → U5 1A (pin 2) → U5 1Y (pin 3) → R17 33 Ω → DATA → U3 SER IN (pin 3), J2 pin 4, J3 pin 4.
SRCK: U1 GPIO18 (pin 24) → U5 2A (pin 5) → U5 2Y (pin 6) → R18 33 Ω → SRCK → U2/U3 pin 13, J2/J3 pin 5.
RCK: U1 GPIO17 (pin 22) → U5 3A (pin 9) → U5 3Y (pin 8) → R19 33 Ω → RCK → U2/U3 pin 12, J2/J3 pin 6.
Cascade: DATA enters U3 first; U3 SER OUT pin 18 connects to U2 SER IN pin 3.

Table

Check	Result	Evidence
Continuity/topology of all three paths	PASS	Confirmed from live schematic net membership listed above.
U1 3.3 V output meets AHCT input VIH	UNVERIFIED	The architecture is appropriate for TTL-threshold AHCT input, but exact U1 VOH and U5 VIH clauses were not retrieved.
U5 output meets TPIC VIH=0.85·VCC	UNVERIFIED	At VCC=5 V the stated receiver threshold is 4.25 V. Exact guaranteed U5 VOH under the relevant load and TPIC VIH clause could not be cited.
VOL/VIL margins	UNVERIFIED	Exact guaranteed driver VOL and receiver VIL values under applicable currents were not retrieved.
First-shifted byte physical destination	PASS	With U3 first in the serial chain and U2 downstream, after 16 clocks the earliest byte has propagated into U2, which drives DS1. The later byte remains in U3 and drives DS2. This assumes conventional MSB/LSB firmware ordering within each byte.

3. Segment paths and currents

All segment topology is continuous: +12 V → both common-anode pins of each display → LED segment → resistor → corresponding TPIC drain.

Drain assignment

DS1 / U2: A→DRAIN0/R1, B→DRAIN1/R2, C→DRAIN2/R3, D→DRAIN3/R4, E→DRAIN4/R5, F→DRAIN5/R6, G→DRAIN6/R7, DP→DRAIN7/R8.
DS2 / U3: A→DRAIN0/R9, B→DRAIN1/R10, C→DRAIN2/R11, D→DRAIN3/R12, E→DRAIN4/R13, F→DRAIN5/R14, G→DRAIN6/R15, DP→DRAIN7/R16.

Assignment result: PASS against the schematic’s stated segment-role properties.

Current calculations

Ignoring the TPIC drain saturation voltage (not available as cited evidence), current is I=(VS−VF)/R.

Table

Segment type	VS	VF assumption	R	Calculated current	5–20 mA check
A–G, five dies	11.5 V	5×2.0 V	220 Ω	6.82 mA	PASS
A–G, five dies	11.5 V	5×1.8 V	220 Ω	11.36 mA	PASS
A–G, five dies	12.0 V	5×2.0 V	220 Ω	9.09 mA	PASS
A–G, five dies	12.0 V	5×1.8 V	220 Ω	13.64 mA	PASS
A–G, five dies	12.5 V	5×2.0 V	220 Ω	11.36 mA	PASS
A–G, five dies	12.5 V	5×1.8 V	220 Ω	15.91 mA	PASS
DP, one die	11.5 V	2.0 V	1 kΩ	9.50 mA	PASS
DP, one die	11.5 V	1.8 V	1 kΩ	9.70 mA	PASS
DP, one die	12.0 V	2.0 V	1 kΩ	10.00 mA	PASS
DP, one die	12.0 V	1.8 V	1 kΩ	10.20 mA	PASS
DP, one die	12.5 V	2.0 V	1 kΩ	10.50 mA	PASS
DP, one die	12.5 V	1.8 V	1 kΩ	10.70 mA	PASS

All 16 resistor channels use one of these two cases, so none falls outside 5–20 mA under the requested idealized assumptions. Maximum calculated drain current is 15.91 mA, far below the requested 150 mA comparison threshold; the exact TPIC rating and dissipation clause remain UNVERIFIED. Maximum simultaneous sink power cannot be called negligible without a cited drain voltage and thermal model.

4. Power and decoupling

Table

Check	Result	Evidence
U2/U3 power and local decoupling	PASS	VCC pin 2 is on +5 V; GND pins 10/11/19 are on GND. C6 and C7 are each 100 nF from +5 V to GND and assigned by role to U2/U3.
U5 power and local decoupling	PASS	VCC pin 14 is on +5 V, pin 7 is GND, and C5 is 100 nF from +5 V to GND assigned to U5.
U4 basic connectivity	PASS	VI pin 3 is +12 V, VO pins 2/4 are +5 V, GND pin 1 is GND. C1/C2 are input bypass/bulk; C3 is output bulk.
LM1117 capacitor compliance	UNVERIFIED	C3 is specified as 10 µF tantalum with a project note requiring 0.3–22 Ω ESR, but the actual capacitor MPN/ESR over temperature is absent. C2/C3 are generic and polarity is not represented by the selected generic non-polarized symbol.
Tantalum derating	PASS for nominal voltage ratio; UNVERIFIED for vendor rule	C2: 12.5 V maximum request case on 25 V rating = 50% rated voltage. C3: 5 V on 16 V = 31.25%. Actual surge/temperature derating compliance requires capacitor MPN data.
LM1117 dropout/headroom	PASS for nominal architecture	12 V input provides large voltage headroom for a 5 V output; exact dropout at assumed load was not cited.
LM1117 thermal performance	FAIL	Dissipation is approximately `(12−5)×ILOAD`. At 200 mA this is 1.4 W; at 300 mA it is 2.1 W; at 500 mA it is 3.5 W. These levels are severe for SOT-223 without a validated large thermal copper area. The observed dedicated +5 V thermal polygon was reported inactive, so the intended copper heat spreader cannot be credited. Exact junction temperature is UNVERIFIED because actual effective copper area, board thermal stack, ambient, and cited θJA curve were unavailable.
U1 VSYS voltage	PASS for 12 V powered case	U1 VSYS is tied to regulated +5 V, not +12 V.
No U1 pin above 5.5 V	UNVERIFIED	Signal pins connect only to U5 inputs, and power enters VSYS at +5 V. However, dual-source/backfeed behavior can alter +5 V and was not proven safe.

5. Power-state cases

Table

State	Result	Rail behavior / concern
12 V present, USB absent	FAIL	+12 V feeds displays and LM1117; +5 V feeds Pico VSYS, U5, U2, U3. Function is topologically correct, but LM1117 thermal performance is not adequate/validated for Wi-Fi load.
USB present, 12 V absent	FAIL	Pico VBUS can feed VSYS through its onboard power path, placing an approximately USB-derived voltage onto the board +5 V net and therefore U5/TPIC supplies and U4 output. The exact diode drop and resulting minimum rail were not cited, so logic compliance is UNVERIFIED. There is no external reverse-current limiting/isolation shown between +5 V and U4 output; reverse current into the unpowered LM1117 input is not bounded by a schematic component.
Both 12 V and USB present	UNVERIFIED / high risk	The Pico module includes its own VBUS/VSYS power-path behavior, but the external LM1117 hard-drives VSYS/+5 V. No explicit ideal-diode or source-selection element isolates the two sources. Absence of USB back-drive cannot be confirmed.
Power-on before first RCK	FAIL as deterministic-display requirement	/G is permanently low (outputs enabled). /SRCLR is pulled high, so it does not clear the shift register at startup. Before known data are shifted and latched, the output state is not guaranteed by schematic control; visible random/undefined segments may occur.

6. Enable and control logic

Table

Check	Result	Evidence
U5 used-channel enables	PASS	/1OE, /2OE, /3OE are tied to GND.
U5 unused channel	PASS	/4OE and 4A are tied to GND, so the unused input is not floating and its output is disabled only if /4OE high; here /4OE low means 4Y actively drives low. It is electrically defined but unnecessarily enabled.
TPIC output enables	PASS	Both /G pins are tied to GND, enabling drains.
/SRCLR bias	PASS	Shared SRCLR_N connects both TPIC /SRCLR pins through R20=10 kΩ to +5 V.
GPIO17/18/19 SPI suitability	UNVERIFIED	The chosen GPIOs are connected consistently, but the exact Pico 2 W alternate-function table and reset defaults were not retrieved with immutable citation. Firmware can generally select GPIO function, but this cannot be marked PASS under the requested evidence rule.

7. Expansion bus

Table

Check	Result	Evidence
J2/J3 identical pin order	PASS	Both are: 1 +12 V, 2 GND, 3 +5 V, 4 DATA, 5 SRCK, 6 RCK.
Signals and rails provided	PASS	A second panel receives +12 V, GND, +5 V, DATA, SRCK, and RCK. Each logic signal shares the GND return on pin 2.
Can an otherwise identical panel run with U1/U4/U5/J1 absent?	PASS with electrical caveat	The headers provide both power rails and already level-shifted logic, so its TPICs/displays can operate without those upstream parts. It lacks local 12→5 V conversion, controller, input connector, and level shifting, by design.
Same-content behavior	UNVERIFIED	A parallel DATA/SRCK/RCK connection makes both panels receive the same serial stream, but loading, cable length, edge integrity, connector orientation, and firmware timing were not analyzed from physical interconnect specifications.

8. Fresh ERC/DRC results

Review timestamp: 2026-09-01T03:20:30.849Z.

Table

Finding	Result	Classification
J3 overlaps DS1 on Top, 14.39 mm²	FAIL	Real assembly defect: component bodies overlap.
J3 overlaps J1 on Bottom, 2.89 mm²	FAIL	Real assembly/mechanical defect.
J1 edge placement	FAIL	Real connector-placement defect; a board-edge connector must align and orient to the board edge.
Three overlapping-copper findings involving J1/nearby traces	FAIL	Real short/manufacturing risk until geometry is inspected and corrected.
U1 VBUS missing-power ERC	PASS as intentional no-connect	Project role explicitly states VBUS is intentionally unused because the design powers the module through VSYS. This ERC item is intentional in the 12 V-only intended use, though the USB power-state request exposes a separate architecture risk.
Informational component overrides	UNVERIFIED	Overrides are not inherently defects; each affected shape needs manual visual comparison to the intended footprint/model.

The returned filtered check set did not show a current airwire count, dangling-trace result, or all possible DRC categories. Their absence from this result is not a PASS.

Ordered blockers and degradations

Prevents reliable operation or manufacture

J1/J3/DS1 physical overlaps and J1 edge-placement error. Fix by repositioning and orienting J1/J3 against the real board-edge and connector mating geometry, then rerun DRC.
Overlapping copper at J1. Inspect the three reported objects, remove/reshape the offending copper, and reroute; verify no shorts.
LM1117 thermal architecture. Replace the 12→5 V linear stage with a buck regulator, or establish a tightly bounded low load and validate copper/thermal performance. A Wi-Fi Pico load makes the present dissipation impractical.
Uncontrolled USB/12 V source interaction. Add explicit power-path isolation/source selection so USB cannot reverse-feed U4 and the external 5 V source cannot back-drive VBUS.
Unverified 40101B-5 pinout. Obtain the manufacturer drawing or continuity-test a real display before fabrication; correct CA1/CA2/segment pad assignments if needed.

Degrades behavior or verification confidence

Undefined startup display. Control /G and/or /SRCLR from the MCU (with safe pulls), clear and latch before enabling outputs.
Generic tantalum capacitors lack exact MPN, polarity representation, ESR, surge, and derating proof. Select real polarized parts meeting LM1117 ESR requirements across temperature.
Datasheet provenance incomplete. Complete immutable datasheet indexing and independently verify every symbol-to-footprint pad map before release.
Expansion cable integrity unverified. Define cable length, grounding, connector orientation, and edge-rate/termination limits; validate on the longest intended daisy-chain.
Unused U5 channel is enabled low rather than disabled. Tie /4OE high and keep 4A defined, or document why an actively driven unused output is acceptable.

Executive result
1. Pin-map provenance
2. DATA, SRCK, RCK, and cascade
Live signal paths
3. Segment paths and currents
Drain assignment
Current calculations
4. Power and decoupling
5. Power-state cases
6. Enable and control logic
7. Expansion bus
8. Fresh ERC/DRC results
Ordered blockers and degradations
Prevents reliable operation or manufacture
Degrades behavior or verification confidence