Review date: 2026-09-01 Scope: Read-only review of the current schematic and PCB. No fixes were applied. Evidence policy:PASS means confirmed from live project data and, where required, immutable datasheet evidence. FAIL means live project data demonstrates a functional or manufacturing defect. UNVERIFIED means the required external evidence or physical mapping was unavailable. Datasheet indexing returned “immutable evidence not ready” for the TPIC6B595 and SN74AHCT125 queries, so claims requiring datasheet clauses are not promoted to PASS.
Executive result
Overall: FAIL. The schematic signal topology is coherent, but the board has active PCB errors and the 12 V-to-5 V linear-regulator architecture has a severe thermal ri...
Overall: FAIL. Primary blockers are J1/J3/DS1 placement and copper conflicts, LM1117 thermal dissipation, unsafe/unverified USB–12 V power interaction, and the unverified 40101B-5 pinout. No design changes were applied.
Purpose and ImplementationWhat This Board Is Supposed to Do
The Days Since Counter is a large, network-capable two-digit counter intended to show the number of days since a selected event. Typical uses include “days since the last incident,” “days since a milestone,” or any other value that can be represented from 00 to 99.
The Raspberry Pi Pico 2 W provides the intelligence and wireless connectivity. Firmware determines the value to display—either by calculating elapsed days from a stored date or by receiving an updated value over Wi-Fi—and converts the two decimal digits into seven-segment patterns.
The board is designed as a self-contained sign:
A 12 V DC input powers the board.
Two large common-anode seven-segment modules provide the visible digits.
Created Purpose and Implementation. It explains the board’s intended “days since” function, power architecture, Pico firmware role, logic buffering, serial display drivers, LED current paths, expansion bus, and physical PCB implementation.
The Days Since Counter is a large two-digit numeric display controller. It uses two high-current common-anode seven-segment displays, serial power shift-register drivers, and a Raspberry Pi Pico 2 W controller. Two mirrored six-pin headers distribute power and the serial control bus across the full width of the PCB.
The project is still under development: the major parts and display current-limiting networks are present, but most controller, power, buffer, and display-driver connections are not yet completed.
PCB
Board size: 500 mm × 122 mm
Copper layers: 2
Displays: top side
Controller, drivers, regulator, logic buffer, resistors, barrel connector, and expansion headers: bottom side
The display bodies occupy the left portion of the long board. The remaining board area carries large top-side artwork/silkscreen. J2 and J3 are positioned symmetrically about the board's vertical center axis.
Major Components
Table
Designator
Part
Package / mounting
Function
Current state
U1
Raspberry Pi Pico 2 W Shield SMD
Bottom-side castellated/SMD module
Main Wi-Fi-capable microcontroller
Placed, currently unwired
U2
TPIC6B595DWR, LCSC C7094
SOIC-20, bottom
Power shift-register/display sink driver
Only serial cascade connection currently exists
U3
TPIC6B595DWR, LCSC C7094
SOIC-20, bottom
Second power shift-register/display sink driver
Only serial cascade connection currently exists
U4
LM1117IMPX-5.0/NOPB
SOT-223 SMD, bottom
Fixed 5 V linear regulator
Placed, currently unwired; input voltage, load, capacitors, and thermal design remain to be finalized
U5
SN74AHCT125DR, LCSC C155176
SOIC-14, bottom
Quad AHCT tri-state buffer / 3.3 V-to-5 V logic interface
Placed, currently unwired
DS1
40101B-5
Large through-hole display, top
First common-anode seven-segment digit
Segment pins connected to R1–R8
DS2
40101B-5
Large through-hole display, top
Second common-anode seven-segment digit
Segment pins connected to R9–R16
J1
Tensility 54-00164
Bottom-side board-edge barrel connector
DC power input
Placed, currently unwired
J2
1×6 vertical pin header
2.54 mm through-hole, bottom
Right-side power/control bus connector
Fully bused to J3
J3
1×6 vertical pin header
2.54 mm through-hole, bottom
Left-side power/control bus connector
Fully bused to J2
Displays
DS1 and DS2 are 40101B-5 common-anode seven-segment displays. Each has these ten terminals:
Table
Pin
Signal
1
CA1 common anode
2
E segment
3
D segment
4
C segment
5
Decimal point
6
B segment
7
A segment
8
CA2 common anode
9
F segment
10
G segment
Implemented PCB footprint override
The source-part metadata still describes the earlier geometry, but the active PCB layout overrides both placed displays to the corrected physical geometry:
Five pins per row at X positions −10.16, −5.08, 0, +5.08, +10.16 mm
5.08 mm center-to-center pitch
The middle pin of each row remains fixed
Row Y positions remain ±53.50 mm
Every display lead uses a 0.9 mm plated drill
Copper pads remain 2.4 mm circular pads
Segment Current-Limiting Resistors
All segment resistors are 0805 SMD parts on the bottom side, aligned near their matching display pins.
DS1
Table
Segment
Resistor
Value
Existing net
A
R1
220 Ω
Net 1
B
R2
220 Ω
Net 2
C
R3
220 Ω
Net 3
D
R4
220 Ω
Net 4
E
R5
220 Ω
Net 5
F
R6
220 Ω
Net 6
G
R7
220 Ω
Net 7
DP
R8
1 kΩ
Net 8
DS2
Table
Segment
Resistor
Value
Existing net
A
R9
220 Ω
Net 11
B
R10
220 Ω
Net 10
C
R11
220 Ω
Net 14
D
R12
220 Ω
Current schematic connectivity is DS2 D ↔ R12 P1, but the net is unnamed in the current summarized list
E
R13
220 Ω
Net 15
F
R14
220 Ω
Net 12
G
R15
220 Ω
Net 13
DP
R16
1 kΩ
Net 9; currently connected to R16 P2 rather than P1
The free terminal of each resistor is intended to connect to a TPIC6B595 drain output. Those driver-to-resistor connections have not yet been assigned.
Display Drivers
U2 and U3 are TPIC6B595DWR eight-channel power shift registers. Relevant pins are:
VCC: pin 2
SER IN: pin 3
DRAIN0–DRAIN3: pins 4–7
/SRCLR: pin 8
/G: pin 9
GND: pins 10, 18, and 19
SRCK: pin 11
RCK: pin 12
DRAIN4–DRAIN7: pins 13–16
SER OUT: pin 17
The only currently implemented TPIC connection is:
Net 16: U3 SER OUT ↔ U2 SER IN
Power, ground, clock, latch, clear, output-enable, initial serial input, and all sixteen drain-to-segment-resistor connections remain unwired.
The requested architecture indicates the following intended assignments, but they are not yet connected to the TPIC pins:
+5V → both TPIC VCC pins and /SRCLR pull-up
GND → all TPIC ground pins
DATA → first shift register SER IN
SRCK → both shift registers' SRCK pins
RCK/latch and /G/output-enable control sources still need to be selected.
Controller and Logic Buffer
U1 — Raspberry Pi Pico 2 W
U1 is the main controller. It exposes the Pico GPIO, power, SWD, VBUS, VSYS, 3V3, and ground pins. No Pico pins are currently assigned to DATA, SRCK, RCK, /G, or other project nets.
U5 — SN74AHCT125DR
U5 is a quad AHCT tri-state buffer intended to translate Pico 3.3 V logic to 5 V-compatible control signals. It is the exact SN74AHCT125DR, LCSC C155176, in SOIC-14.
VCC: pin 14
GND: pin 7
Inputs: 1A, 2A, 3A, 4A
Outputs: 1Y, 2Y, 3Y, 4Y
Active-low enables: /1OE, /2OE, /3OE, /4OE
U5 is currently completely unwired. A decoupling capacitor is also not yet present.
Power Section
J1 — DC input
J1 is a Tensility 54-00164 bottom-side board-edge DC barrel connector. Its four schematic terminals are currently unnamed A1, A2, B, and C variants and are not connected to +12V or GND.
The connector pin function/polarity must be confirmed from its datasheet before wiring.
U4 — 5 V regulator
U4 is a Texas Instruments LM1117IMPX-5.0/NOPB fixed 5 V regulator in SOT-223.
GND: pin 1
VO: pin 2 and thermal tab pin 4
VI: pin 3
U4 is currently unwired. Required input/output capacitors are not present. Before completion, the design needs:
Confirmed J1 input voltage and polarity
Total 5 V load budget
LM1117 dropout/headroom check
Thermal dissipation calculation
Datasheet-compliant input and output capacitors
Adequate copper area on the output/tab for heat spreading
J2 and J3 Bus Connectors
J2 and J3 are identical 1×6, 2.54 mm-pitch vertical through-hole headers. They have the same pinout and matching pins are directly connected across the board.
Table
Pin
Net
Intended function
1
+12V
Display common-anode supply
2
GND
TPIC grounds and supply return
3
+5V
TPIC VCC and /SRCLR pull-up supply
4
DATA
Serial data into the first TPIC
5
SRCK
Shift clock bus to both TPICs
6
GND
Signal return
Placement and routing
J3 center: (−232.0384, −31.3935) mm
J2 center: (+232.0384, −31.3935) mm
Both are on the bottom side with matching orientation
J2 is the exact vertical-axis mirror position of J3
All six matching pin pairs are connected with individual straight bottom-layer traces
Trace width: 1.0 mm
Trace length: approximately 464 mm each
The two GND pins have separate parallel traces
These are the only completed PCB routes currently present.
Current Netlist
Table
Net
Connected pins
+12V
J2 pin 1, J3 pin 1
GND
J2 pins 2 and 6, J3 pins 2 and 6
+5V
J2 pin 3, J3 pin 3
DATA
J2 pin 4, J3 pin 4
SRCK
J2 pin 5, J3 pin 5
Net 1
DS1 A, R1 P1
Net 2
DS1 B, R2 P1
Net 3
DS1 C, R3 P1
Net 4
DS1 D, R4 P1
Net 5
DS1 E, R5 P1
Net 6
DS1 F, R6 P1
Net 7
DS1 G, R7 P1
Net 8
DS1 DP, R8 P1
Net 9
DS2 DP, R16 P2
Net 10
DS2 B, R10 P1
Net 11
DS2 A, R9 P1
Net 12
DS2 F, R14 P1
Net 13
DS2 G, R15 P1
Net 14
DS2 C, R11 P1
Net 15
DS2 E, R13 P1
Net 16
U3 SER OUT, U2 SER IN
Incomplete or Unresolved Work
Connect J1 to +12V and GND after confirming barrel-jack polarity.
Wire U4 between +12V and +5V with required capacitors and thermal copper, after validating dissipation.
Connect both display common-anode pins to +12V as intended.
Connect U2/U3 drain outputs to the free ends of R1–R16.
Connect +5V and GND to U2, U3, and U5.
Connect DATA and SRCK through U5 or directly, depending on the final control architecture.
Assign Pico GPIOs for DATA, SRCK, RCK, /G, and optional /SRCLR control.
Add the U5 decoupling capacitor and appropriate TPIC decoupling/bulk capacitors.
Define /SRCLR pull-up and safe default for /G.
Rename generic segment nets to descriptive names.
Resolve the DS2 D net naming omission and confirm the deliberate R16 P2 connection.
Route the remaining 16 airwires and run full ERC/DRC.
Update the 40101B-5 source part so its stored metadata matches the active 5.08 mm-pitch, 0.9 mm-drill layout override.
Overall Architecture
Diagram
The diagram shows the intended architecture. Only the display-to-resistor connections, U3-to-U2 serial cascade, and J2-to-J3 bus routes currently exist electrically.