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Fabricator Assembly Handoff
Controlling release update — 24 September 2026, final verification
This section supersedes the older U6-clearance and missing-MPN holds retained below as audit history. The U6 5V_MAIN-to-SW clearance was repaired to 0.100 mm, above the configured 0.0889 mm minimum. The final U6/L2 optimization was independently rechecked in the live project. Current results: 0 airwires, 0 redundant traces, and no open/error/warning findings for overlapping or dangling copper, invalid layers, keepouts, component overlap, stackup validation, pad-access clearance, or switching-power-stage checks. FPGA routing remains intact.
All 19 previously held passive placements now have assigned orderable MPNs; the live manufacturing review reports 0 missing-MPN findings. The current BOM, Gerber, PnP, and test-netlist exports must be regenerated from this final revision; any earlier conversation exports are obsolete.
Current disposition: ready for manufacturing quotation and supplier CAM/DFM review. Production release remains conditional only on the selected supplier accepting the specified 0.45 mm pad / 0.20 mm drill through-vias and Type VII capped via-in-pad process, plus accepting or dispositioning the documented hand-wire traveler. These are supplier/process confirmations, not unresolved CAD routing defects.
Engineering release status — 24 September 2026
HOLD — NOT ORDER-READY, EVEN THOUGH ROUTING HAS ZERO AIRWIRES. A targeted independent check identified a top-layer 0.50 mm 5V_MAIN segment from (−23.42, 7.75) to (−23.42, 7.08) mm only approximately 0.020 mm copper-edge distance from the unlike-net U6 SW pad, against the configured 0.0889 mm minimum clearance. The selected automated DRC checks did not flag this calculated geometric gap; do not infer manufacturing clearance from zero DRC findings. The attempted local rule edits were reverted to checkpoint #03098a4a; no repair was retained because shifting this one segment alone disconnects its VIN path. Require independent Gerber/CAM measurement and a continuous, rechecked local VIN reroute if confirmed, before release. Do not relax the minimum rule to hide this issue. Also resolve the U6→L2 switching-stage placement error: reported route 6.9 mm versus direct 3.3 mm (2.10×), feedback path in the corridor. Do not blindly move L2 or modify the completed FPGA fanout; select/verify L2 and review a compact switch-loop reroute with fresh connectivity, DRC and noise assessment. These are additional engineering holds independent of the manual-wire and MPN holds below.
CURRENT revision-specific hand-wire traveler — HOLD for shop disposition (24 September 2026)
Controlling instruction for the current CAD revision, not order authorization. Record the PCB/assembly revision and serial on the shop traveler and match it to the independently checked artwork, BOM, pick-and-place (PnP), and netlist. Live CAD audit: 0 airwires, 0 redundant traces; these counts do not prove any physical hand-wire connection or make the board manufacturing-release ready. Obtain written shop acceptance of every landing, wire route, solder-mask opening, strain relief, probe access and test method before placing an order or fitting wires. The 15 R-designators below are schematic representations of manual bridges, not copper routes or automatically placed resistors. The netlist records intended electrical connectivity; PnP covers automatic population and does not install these links; only the signed manual traveler records physical fits. Do not infer installed parts or exposed solderable surfaces from CAD.

Table

Traveler itemWire from → toPre-fit hold / special condition
R26TP5 ↔ TP9TP9 reserved for this wire only.
R34TP11 ↔ TP14Confirm access after population.
R35TP25 ↔ TP26Shared TP26: three separate wires total.
R38TP27 ↔ TP28TP27 two wires; TP28 three.
R65TP29 ↔ TP26Shared TP26.
R66TP30 ↔ TP26Shared TP26.
R67TP31 (U2 PA15/38) ↔ TP28Shared TP28; PA4 is not this endpoint.
R68TP32 ↔ TP28Shared TP28; confirm edge clearance.
R69TP33 (U2 PB4/40) ↔ TP15 (21.25, −30.77 mm)TP15 is same-net large 4.7 × 3.43 mm top copper, but its 5018 footprint has Exclude from BOM=true: whether 5018 is fitted or bare pad, solderable exposure, solder mask, strain relief and retained MISO probe access are unresolved. No fallback to double-fitting TP9. PA6 is not this endpoint. TP9/J5:9 net routing also uses Mid-Layer 5: do not describe the whole route as top-copper-only.
R70TP34 ↔ TP35Reset bridge; historical Reset Wire ECO is not the current build traveler.
R71U2 PA13/pin 34 ↔ J4:2HOLD: STM32F411CEU6 UFQFPN package has no verified exposed solderable PA13 lead after population; do not call it gull-wing or instruct soldering a lead. Shop must verify an accessible approved landing or request redesign before fit.
R72U2 PB1/pin 19 ↔ R25:P1HOLD: same unverified UFQFPN access. R25 is a physical axial 0 Ω jumper without an approved MPN; its P1 is the proposed wire termination. Confirm R25's actual fit, solderable joint, insulation and mechanical access or redesign before fit.
R73TP17 ↔ TP19Preserve probe access and approved FPGA debug remap.
R74TP27 ↔ TP22Second TP27 wire; preserve probe access and FPGA CS remap.
R75TP21 ↔ TP20Preserve probe access and FPGA gate remap.
Hard landing hold: TP26 and TP28 each take three wires and TP27 takes two on 0.7 × 0.9 mm lands. No multiwire joint technique has been qualified. Require documented shop fit/strain-relief/inspection signoff or redesign with larger landings, then regenerate/recheck the revision; do not simply stack or prescribe a fitting procedure. Independently resolve U2 PA13/PB1 access, TP15 5018-versus-bare-pad state, R25 jumper procurement/fit and all other endpoint accessibility before order or wire installation. These are distinct holds even with zero CAD airwires.
Execution sequence only after those holds clear: (1) identify revision and inspect/test the bare fabricated board first, including bare-board electrical test to the revision-matched copper/test netlist and adjacent-net isolation; distinguish that copper-only test from schematic connectivity across not-yet-fitted wires. (2) Inspect actual population, record R25 and TP15 state, mark up accessible wire sites and path, then have the shop sign the wire-fit traveler. (3) Fit only approved insulated bridges, inspect each solder joint, wire dressing and mechanical strain relief, and leave test points probe-accessible. (4) With all power removed, record each fitted link's endpoint-to-endpoint continuity to its correct intended net plus isolation from adjacent unrelated nets (including neighboring pads and rails), test the finished board against the approved as-built network, and photograph/sign off each link and shared land. There are 30 wire terminations at 25 distinct sites, plus R25's separate joints; these counts are inspection workload, not evidence of physical fit. Stop on failed continuity/isolation, missing access or failed inspection; repair under approved disposition and repeat impacted tests before powered bring-up. No powered step until the separate bring-up gates pass.
Procurement is also held: the remainder is the 19 physical missing-MPN placements itemized below (7 rail capacitors C52/C53/C56/C58/C59/C60/C64; L1/L2; R3–R8; R64; R13/R16; R25), not these 15 manual-wire links. R62/R63 have assigned MPNs, not electrical/assembly approval. Reconcile latest BOM, exceptions, fitted jumper, drawing and PnP by designator before release; do not treat this list as a substitute for fresh live BOM/DRC/ERC or supplier qualification.
Status: quote/review package only — NOT fabrication or assembly order authorization. Snapshot of live project inspected 24 September 2026. Preliminary Gerber/drill, BOM variants, pick-and-place variants, and IPC-D-356 were exported in the project conversation for quoting/review, but have not been approved for production or ordered. No fabricator acceptance or physical validation has been documented. Seek separate PCB fabrication and PCBA/hand-wire quotations; do not use the preliminary exports as released artwork.
Held passive procurement update — 24 September 2026
The physical missing-MPN review changed 21 → 19. Only R62 and R63 were assigned manufacturer/MPN; no value, footprint, wiring or PCB edit was made. These are procurement identities, not electrical validation or assembly release. Both are existing 0402 (1005 metric) USB_VBUS-to-GND divider parts: R62 4.7 kΩ = Yageo RC0402FR-074K7L and R63 10 kΩ = Yageo RC0402FR-0710KL. Yageo's exact-part specifications confirm each resistance, ±1% tolerance, 0402 1.00 × 0.50 mm body and 0.063 W rating at 70°C; the RC-series datasheet confirms the 0402 1/16 W, 50 V standard version and dimensions. With a nominal 5 V USB input, divider current is 5/14.7k = 0.340 mA, powers R62 ≈ 0.54 mW and R63 ≈ 1.16 mW; even 5.5 V for a comparative calculation gives 0.374 mA / 0.66 mW / 1.40 mW. Confirm actual USB VBUS limits and PA9 input tolerance separately: the resistor sourcing does not certify the sense voltage. Exact-part maker sheets: https://yageogroup.com/component-documentation/download/specsheet/RC0402FR-074K7L and https://yageogroup.com/component-documentation/download/specsheet/RC0402FR-0710KL.
19 remaining physical, neither DNP nor schematic-only: C52, C53, C56, C58, C59, C60: each 10 µF, SMD_0805_2012Metric, across 5V_MAIN/GND; C64: 4.7 µF, SMD_0603_1608Metric, across 5V_MAIN/GND. All seven stay held: require exact candidate MPN manufacturer C(V,T) DC-bias curves/table including tolerance, temperature, aging and voltage rating at the highest permitted 5V_MAIN (including protection-stage excursion), then compute each effective capacitance and compare the combined 5 V rail transient/hold-up and each regulator's minimum input-capacitance requirement. No effective µF figure is defensible yet: C_eff = C_nom × measured/manufacturer bias-retention at V_work × tolerance/temperature/aging factors, not nominal 64.7 µF. Alternatives: an evidenced drop-in same-value/same-land MLCC, or escalate rail-capacitance/footprint redesign for separate approval; do not silently change size/value.
L1: 470 nH, SMD_1210_3225Metric, U4 TPS62826 1V1_SW→1V1; L2: 1 µH, same footprint, U6 TPS621351 3V3_SW→3V3. Both held pending a physical 1210 inductor manufacturer's exact land/terminal drawing, L versus DC current, DCR, temperature-rise/Irms and saturation definition/limit, plus actual FPGA/other load profile and permitted 5V_MAIN range. Buck CCM illustration only at Vin=5.0 V and typical fSW (not a worst-case certificate): ΔIL = Vout(1−Vout/Vin)/(L·fSW), Ipk = Iout+ΔIL/2. U4 1.1 V / 0.47 µH / 2.2 MHz gives ΔIL≈0.381 A, Ipk≈Iout+0.191 A (at schematic 1.5 A target: ≈1.691 A); U6 3.3 V / 1 µH / 2.5 MHz gives ΔIL≈0.449 A, Ipk≈Iout+0.224 A. TI lists the respective typical PWM frequencies (2.2 MHz for U4, 2.5 MHz for U6), but no specified minimum fSW for either; these figures must not size saturation at a guarantee. U4's datasheet allows 3 A and U6's 4 A maximum output; these IC ceilings are not a measured FPGA load. Determine Iout continuous/peak from the actual fabric bitstream and other loads, high Vin and low frequency/low L worst case and transient limit before comparing guaranteed Isat and thermal Irms. If no same-land inductor meets margins, seek approved footprint/inductance redesign rather than assign a convenient MPN.
R3 300 kΩ, R4 1.05 kΩ, R5 83.3 kΩ, R6 100 kΩ, R7 560 kΩ, R8 150 kΩ (all SMD_0402_1005Metric) remain held as eFuse enable/current-limit, buck feedback and bias: exact 1%-or-better MPN/rating must be checked against U7/U4/U6 data-sheet threshold/error budgets, startup, resistor power and the actual rail; do not infer from the shared RC family or MPN spelling. R64 59 kΩ (SMD_0402_1005Metric) sets TPS2121 ILM: hold until TI's threshold/current-limit tolerance across resistor tolerance and power at the actual source budget is verified. R13 and R16 499 Ω (SMD_0402_1005Metric) each strap CFGMDN2/CFGMDN0 to ground: despite an existing Yageo 499 Ω ±1% 0402 part, its possible 503.99 Ω upper tolerance exceeds the recorded below-500 Ω strap requirement; require an approved worst-case interpretation or redesigned strap value by separate change request before assigning an MPN. R25 0 Ω H_AXIAL-P7.62_D2.5 is a physical hand-fit reset jumper: hold for a manufacturer axial jumper drawing with body ≤2.5 mm, 7.62 mm hand-formable lead span, drill/lead compatibility, insulation, and approved hand-fit/current traveler; a 6.3 mm-body candidate alone is not a mechanical release.
The remaining MPN findings above are 19 actual placements, not optional DNPs. Conversely R26/R34/R35/R38 and R65–R75 are schematic-only manual-wire ECO links, not substitute SMT or DNP passives; retain separate wire instructions above. Retest the live BOM/DRC/ERC at release; a reduced missing-MPN count is not an electrical or fab pass.
Paste into a quote request
Please quote a small first-article run of a 100 × 100 mm, rectangular, eight-copper-layer FPGA validation PCB, nominal CAD stackup approximately 1.46 mm, each copper layer nominal 0.035 mm. Quote bare-board fabrication separately from SMT/through-hole assembly and hand-fitted wire ECO operations. The board has a 0.80 mm-pitch 381-ball FPGA BGA and pad-overlapping plated through-vias requiring IPC-4761 Type VII: nonconductive resin fully filled, planarized and copper capped on both outer faces before final finish; open, tented or merely plugged vias are unacceptable. Default through via: 0.60 mm capture pad / 0.30 mm drill. Three local overrides: 0.45 mm pad / 0.20 mm drill at PROGRAMN (-11,-6.8) mm [via-in-pad], DONE escape (-11,-8.9) mm, and DONE transition (-6.5,-9.9) mm. Please review these as through-vias across the actual finished thickness, specifically the smaller drill aspect ratio, finished-hole and annular-ring/registration capability, BGA pad registration, Type VII process yield, electrical test, and allowable fab tolerances. Confirm in writing the proposed material/actual 8-layer buildup, finished thickness and tolerance, copper weights (base versus finished/plated), drill definition (tool versus finished), solder mask/finish and impedance capability; do not silently alter drill, pads, stackup, board thickness, BGA land geometry or via fill. Identify NRE, yield implications, lead time and any panelization constraints. If a capability is unavailable, return an exception for design review/redesign and re-export; do not substitute a standard non-capped via process or change geometry without approval. For PCBA quote a BGA-capable stencil/reflow process, moisture-sensitive-device handling per the actual component requirements, first-article X-ray of U1 solder balls and VIPPO region, polarized/connector inspection, documented hand-wire fitting and continuity/isolation testing. State whether your shop can do all stages or which stages need separate vendors. This is an RFQ, not a purchase order or approval to manufacture.
Ask the fabricator to resolve before release: actual layer order/reference planes versus the CAD order (Top signal / Mid1 GND / Mid2 signal / Mid3 power / Mid4 power / Mid5 signal / Mid6 GND / Bottom signal); dielectric thickness/Er availability; eight-layer registration and minimum annular ring for 0.45/0.20; through-drill aspect ratio against finished thickness (nominal 1.46/0.20 ≈ 7.3:1, confirm actual plated/finished geometry); filled-via cap planarity under the BGA, solder-mask registration, IPC Type VII inspection criteria, 0.80 mm BGA assembly clearance, controlled-impedance requirement and coupon/test approach if specified at release. Do not assume a generic 8-layer service reproduces the CAD dielectric recipe. Review proposed surface finish with BGA assembler; do not treat the CAD's paste-layer PbSn labeling as an approved surface finish or alloy choice.
What to inspect and finalize before release (preliminary exports exist in the conversation)
  • Bare-board fabricator: revision-locked Gerber copper (all eight layers), solder mask/silk/outline, plated and nonplated drill files with drill map and local 0.20 mm overrides called out; approved stackup/lamination, via-fill/cap fabrication drawing and tolerances, surface finish, quantity, electrical test to released netlist. IPC-D-356 netlist is optional if both sides support it, but specify the electrical-test basis. Obtain formal CAM/DFM approval and mark three special vias and all pad-overlapping VIPPO in the fab notes.
  • PCBA shop: revision-matched procurement BOM with manufacturer MPN, maker, value, package, quantity, alternates only if engineer-approved, DNP/hand-fit status; top/bottom centroid PnP including rotation, footprint side and origin; solder-paste Gerber/stencil data plus aperture review for the BGA and fine pitch, assembly drawings with polarity/pin-1, hand-wire drawings and test points, reflow/MSL handling and inspection/acceptance criteria. Ask the assembler to confirm BGA stencil/paste and X-ray feasibility, first-article photos/X-ray report, electrical-test disposition and labor for each manual wire. Provide test/firmware artifacts separately only after board-specific build approval.
  • Hand operation is separate from PCB copper and automatic PnP: all schematic ECO links below are excluded from PCB and Pick & Place; do not convert their inherited 0402/0603 package labels into SMT resistor placements. The four DWL-4P28X5P75-0R entries are custom schematic-only wire representations despite their MPN-like label. R25 is different: a real 0 Ω axial jumper with a PCB footprint, to be explicitly procured and hand populated, not omitted with the ECO links. PCB test before wire fitting and assembled test after wire fitting check different connectivity.
Mandatory manual-wire worklist from live schematic
Use insulated fine-gauge wire, dress clear of exposed copper/ports/hot areas, provide strain relief, inspect joints under magnification. Test unpowered endpoint-to-endpoint continuity (target <1 Ω after lead-resistance subtraction for a short link, unless the assembler agrees a justified alternate) and isolation from neighboring power/GND and adjacent unrelated nets; document each link's photo and results. The named test lands are on the associated live schematic nets; route/physical endpoint access must still be verified on the released assembly drawing. No link is implemented by an SMT zero-ohm resistor.

Table

LinkHand-fit endpoints / intended bridgeSpecific validation
R26TP5 FPGA MISO ↔ TP9 HOST_SPI_MISO (also TP15/J5:9 on destination net)U1:PT54A ↔ J5:9 continuity.
R34TP11 FPGA MOSI ↔ TP14 MCU MOSIU1:PT56B ↔ U2:PA7.
R35TP25 FPGA SCK ↔ TP26 central SCKU1:PR89A ↔ TP26.
R38TP27 FPGA CS ↔ TP28 central CSFPGA-CS island ↔ R22/TP28; verify CS function after R74.
R65TP29 (U2:PA5 SCK) ↔ TP26U2:PA5 ↔ central SCK.
R66TP30 (J5:7 SCK) ↔ TP26J5:7 ↔ central SCK.
R67TP31 (U2:PA15 CS) ↔ TP28U2:PA15 ↔ central CS.
R68TP32 (J5:10 CS) ↔ TP28J5:10 ↔ central CS.
R69TP33 at (27.25, 23.10) mm, U2 PB4/40 ↔ TP15 at (21.25, −30.77) mm, 5018 site with 4.70 × 3.43 mm top pad on HOST_SPI_MISOTP15→TP9/J5:9 same-net continuity; route to J5:9 includes Mid-Layer 5, not top only. Verify as-built TP15 fitted-versus-bare state, mask opening, solderability, MISO probe access and strain relief. TP9 is R26-only.
R70TP34 ↔ TP35, insulated wire, reset gapD3:A/J5:6 ↔ FPGA_RST_N/R25:P2; current traveler controls, historical Reset Wire ECO does not authorize fitting.
R71U2 PA13/pin 34 ↔ J4:2, proposed wireHOLD: UFQFPN solderable endpoint after population not established; shop-confirm accessible landing or redesign.
R72U2 PB1/pin 19 ↔ R25:P1, proposed wireHOLD: same UFQFPN access issue; R25 physical axial jumper also held for MPN and fit.
R73TP17 ↔ TP19, insulated 30 AWGHOST_SPI_IRQ ↔ U1:PT20A/DBG_TICK_START; FPGA IRQ remap, standalone DBG_TICK_START unavailable.
R74TP27 ↔ TP22, insulated 30 AWGFPGA CS ↔ U1:PT15A/HEARTBEAT; FPGA CS remap, standalone HEARTBEAT unavailable.
R75TP21 ↔ TP20, insulated 30 AWGDBG_GATE_ALL ↔ U1:PT18A/DBG_TICK_DONE; gate remap, standalone DBG_TICK_DONE unavailable.
Wiring authorization gate: R69 Role Details now correctly specifies TP33 (U2:PB4) → TP15 (HOST_SPI_MISO); PA6 is no-connect. CAD confirms the listed TP5/TP9/TP11/TP14/TP25–TP35/TP17/TP19–TP22 endpoints exist on the top face; this is not proof of after-population iron access, mask exposure as fabricated, path clearance or wire mechanical retention.
R69 alternate landing disposition (supersedes older candidate/hold language below): TP15's dedicated 5018 test-point land is on the same net as TP9/J5:9 on HOST_SPI_MISO; routing to J5:9 also uses Mid-Layer 5. The single-wire R69 destination is TP15, with TP9 reserved for R26.
Before quoting labor/order, mark up a released top-side assembly drawing for R26/R34/R35/R38/R65–R69 with accessible exposed lands, neighboring-component and copper clearance, insulated wire dressing and strain relief. R26 alone goes to TP9, R69 to TP15; never double-fit TP9. TP32 lies near the board edge (center 10.16, 48.50 mm); verify inboard dressing and edge clearance. Follow the current R70 traveler, not the historical reset ECO. R71/R72 target U2 PA13 pin 34 and PB1 pin 19 respectively, but UFQFPN access after population is unverified: hold for shop-approved solderable landings or redesign; confirm J4:2 and R25:P1 terminations independently.
Release-gate clarification: R69's Role Details and intended TP33→TP15 landing now agree with the live nets. For release, approve the separate TP33→TP15 wire-fit traveler, inspect the actual 5018 test-point termination and retained probe access, and record physical continuity/isolation. Do not authorize a double-wire TP9 joint. No purchase/order or fitting is authorized by CAD-only 0/0 routing.
Snapshot and release gates
Live inspection: 197 schematic components, 182 layout footprints, 175 BOM instances / 25 grouped part types, 0 airwires and 0 redundant traces; layout 100 × 100 mm, eight layers. Counts differ because non-board/manual-wire items and BOM exclusions exist; reconcile per designator and exclude flags rather than treating every difference as a missing footprint. The manufacturing review now reports 19 missing-MPN error findings: 105 placements received MPNs since the earlier 124-error snapshot, including two in this update; the remaining 19 require engineering confirmation, not guessed substitutions. The BOM is not procurement-ready for full automatic assembly.
Before any purchase order or manufacturing-data release: (1) select fab and PCBA suppliers, obtain written stackup, drill/annular-ring, special-via Type VII, BGA and CAM acceptance or redesign/re-check if not possible; (2) approve exact U1/other device MPNs, fill missing MPNs/ratings and approved substitutes, reconcile BOM versus PCB/PnP/DNP and every hand-fit wire, inspect footprints/pad numbering/polarity and PnP origin/rotations against actual packages; (3) confirm TP33→TP15 R69 wire joint/5018 physical access, secure dressing, retained probe access and post-fit test traveler, with TP9 reserved for R26; (4) freeze a revision, regenerate Gerber/drill/paste/BOM/PnP/assembly drawings from the same revision, compare layers/drills/outline and drill map in an independent viewer, rerun full DRC/ERC and CAM/DFM, arrange netlist electrical test and X-ray first article; (5) rebuild and validate FPGA bitstream against the board's actual pin constraints and wrapper, not the old unconstrained BIND_8C_ECP5_85.bin (unusable as a board image); establish staged bring-up tests before power. Only after all exceptions are signed may the owner issue an order. First articles require actual rail/JTAG/configuration, reset/SWD/Host-SPI testing and BGA X-ray; no such physical validation exists yet.
References: Fabrication Notes · Routing Completion · Reset Wire ECO · Project Specification (historical intent).

  • Controlling release update — 24 September 2026, final verification

  • Engineering release status — 24 September 2026

  • CURRENT revision-specific hand-wire traveler — HOLD for shop disposition (24 September 2026)

  • Held passive procurement update — 24 September 2026

  • Paste into a quote request

  • What to inspect and finalize before release (preliminary exports exist in the conversation)

  • Mandatory manual-wire worklist from live schematic

  • Snapshot and release gates