Project Start

flux

Batch completed with 3 net reductions: 99 → 96 airwires.
  • Moved and rotated C82 beside U8.
  • Routed MUX_SS locally with a 0.87 mm trace.
  • Routed three FPGA ground links.
  • No blocking copper, layer, via, or protected-region DRC errors remain.
  • Additional candidates were congestion-blocked and skipped without retries.
The next batch should target five trace-to-trace/local 3.3 V branches rather than the now-blocked BGA ground paths.
god2you

god2you

I have 3.1 ACUs left. Knock out the next 5 so we can handoff to my team member who will continue in my place

flux

I’ll make one bounded handoff batch: target five accessible local 3.3 V branches, stop after five persisted reductions, then report the exact airwire/DRC state for your team member.

flux

Handoff batch exceeded the target: 96 → 90 airwires.
Routed/merged:
  • MCU VDD3 decoupling branch
  • Two local 3.3 V pull-up branches
  • 2.5 V regulator output network
  • 5 V regulator input network
  • 3.3 V test-point/capacitor network
Final blocking DRC check: clean—no copper overlap, trace overlap, invalid-layer, via, or protected-region errors.
Team handoff state: 90 airwires remain. Prioritize local trace-to-trace 3.3 V branches, then FPGA ground/rail connections. Avoid the congestion-blocked PGOOD and BGA paths until surrounding routes are cleared.
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Project Specification
Project Overview
Status: Review
First physical validation board for the fixed BIND_8C fabric on LFE5U-85F-6CABGA381. The board will power, configure, observe, and exercise the existing FPGA architecture; it will not redefine BIND computational semantics.
Intended Use
  • Laboratory bring-up and measurement.
  • Direct JTAG validation before the host protocol is complete.
  • Host-driven configuration, tick, gating, readback, and storage experiments.
  • Prototype validation build, not production intent.
Locked Computational Target

Table

ItemLocked value
FabricBIND_8C
FPGALFE5U-85F-6CABGA381
Topbind_fabric_8c
Clusters8 x rcf1_fabric_seq
Active PE512
Edge capacity2,048
StateQ8.8 signed 16-bit
Config address13-bit: cluster [12:10], local [9:0]
Existing bitstreamBIND_8C_ECP5_85.bin
Bitstream SHA-2561ba2a870e1e0562424a48e8ef992b6d7fd1b2b4256730b644829e46bbc590a3b
Existing final routed Fmax62.91 MHz at 25 MHz target
Existing top-level I/O124 bits, unconstrained/autoplaced
The supplied bitstream proves synthesis, placement, routing, and packing on ECP5-85, but is not the final board image because no physical ball constraints were applied.
What the Device Should Do
  • Reliably power and configure the FPGA.
  • Boot a newly re-P&R board-specific image from SPI flash or JTAG.
  • Preserve the existing BIND_8C port semantics.
  • Let a USB host exercise the fabric through a narrow FPGA-side bridge wrapper.
  • Provide practical prototype persistent storage.
  • Expose important runtime signals and all major rails for measurement.
  • Retain raw-interface access independently of the host bridge.
Main Features
  • ECP5-85 FPGA in 381-ball CABGA.
  • Master-SPI configuration flash.
  • Independent JTAG header.
  • USB-C device connection to a USB-capable host MCU.
  • SPI host-to-FPGA wrapper link.
  • microSD prototype persistent storage on the host MCU side.
  • Raw validation connectors and test points.
  • Power, configuration, heartbeat, tick, and fault indicators.
  • Expansion connectors for future body/robotics interfaces.
  • Reset/program controls and thermal provisions.
System Architecture
Diagram
Rendering diagram...
Hardware Subsystems
FPGA Compute
  • Exact device remains LFE5U-85F-6CABGA381.
  • Existing RTL top exposes 124 signal bits.
  • No remote-contribution router, LPID engine, package verification, or USB/SPI wrapper exists in the supplied top.
  • effort is cluster-0 output in the current RTL.
Host Communication
  • Architecture decision: use a USB-capable MCU and USB-C device connector.
  • Use a narrow SPI register protocol between MCU and a thin FPGA top-level wrapper.
  • The wrapper translates serialized host transactions into the unchanged BIND buses and controls.
  • This wrapper is an integration layer, not a change to fabric semantics.
  • Directly driving the 124-bit fabric bus from the MCU is rejected as impractical.
Persistent Storage
  • First board: removable microSD controlled by the host MCU.
  • The logical 50 TB system-level target is not implemented on this PCB.
  • Reserve an expansion path for a future high-capacity host/SBC storage module.
FPGA Configuration and Debug
  • Master-SPI flash for autonomous boot.
  • Independent JTAG remains accessible regardless of the host MCU.
  • Bank 8 and configuration peripherals use one compatible I/O voltage; preliminary choice is 3.3 V.
  • Provide PROGRAMN, INITN, DONE, configuration clock/data, and mode-strap observability.
Clock and Reset
  • 25 MHz low-jitter LVCMOS oscillator on a valid PCLK-capable FPGA ball.
  • No FPGA PLL is required for the initial 25 MHz image.
  • Manual reset, MCU-controlled fabric reset, and FPGA PROGRAMN control are separated.
Debug and Expansion
  • Full raw 124-bit exposure, if retained, uses high-density mezzanine/debug connectors rather than ordinary 0.1-inch headers.
  • Simple headers/test points expose sensor_a, sensor_b, effort, tick_start, tick_done, gate_all, clock, reset, and selected cluster status.
  • Add rail test points and power-good visibility.
Interfaces and Connections
Locked Fabric Ports
clk, rst_n, cfg_addr[12:0], cfg_wdata[15:0], cfg_we, cfg_re, cfg_rdata[15:0], sensor_a[15:0], sensor_b[15:0], effort[15:0], tick_start, tick_done, gate_all, clusters_done_oh[7:0], and n_clusters_ro[15:0].
Preliminary physical signals: SPI clock, controller-to-FPGA data, FPGA-to-controller data, chip select, interrupt/status, FPGA reset, and optional ready/flow-control.
External Interfaces
  • USB-C USB 2.0 device/data and board power input.
  • JTAG header with reference voltage and ground.
  • microSD socket.
  • Raw fabric mezzanine/debug connectors.
  • Future expansion: SPI, I2C, UART, CAN-ready GPIO, power, and grounds.
Power and Runtime Expectations
  • USB-C 5 V is the preferred input.
  • Include input ESD, overcurrent, reverse-current/backfeed protection, and CC current-advertisement handling.
  • Do not assume 3 A is available without detecting the source advertisement.
  • Provide an auxiliary protected 5 V input for bench bring-up and high-load testing.
Power Tree and Power Budget
Diagram
Rendering diagram...
The regulator current ratings are intentionally not locked yet. Final sizing requires a Lattice power-calculator run using the board-constrained design, switching activity, configuration current, and environmental assumptions. Power budgeting must cover startup, configuration, and maximum dynamic load.
Preliminary I/O Bank Strategy
  • Operate all used general-purpose banks at 3.3 V for the first board, matching the current LVCMOS33 port intent and simplifying connectors.
  • Reserve Bank 8 for sysCONFIG/JTAG and avoid consuming its dual-purpose configuration pins as normal BIND I/O.
  • Put clk on a PCLK-capable ball in a lightly loaded bank.
  • Keep buses contiguous by bank: configuration address/control, configuration data write, configuration data read, sensors, effort/status.
  • Keep FPGA outputs away from the oscillator and configuration pins where practical.
  • Exact LOCATE assignments remain blocked until the official ECP5-85F-CABGA381-DD pinout CSV is ingested and checked.
PCB and Stackup Expectations
  • Recommended: 8-layer controlled-impedance board for first-spin routing margin and power integrity.
  • Suggested layer intent: signal / GND / signal / power / power / signal / GND / signal.
  • Solid adjacent ground reference for USB and clock routing.
  • 0.8 mm pitch CABGA escape must be reviewed with the selected fabricator before routing.
  • Place all FPGA decoupling close to its associated balls and feed rails from planes. The hardware checklist requires VCCIO banks to use a valid rail rather than being left open.
  • VCCIO banks support 1.2 V to 3.3 V according to the selected I/O standard.
  • Place the clock only on a pin identified as PCLK/GPLL capable in the official pinout.
  • Power should be delivered from planes and local 100 nF decoupling placed close to power pins.
Manufacturing and Assembly Expectations
  • Professional assembly required for the 381-ball BGA.
  • X-ray inspection recommended for first articles.
  • Use currently obtainable parts and avoid silent substitutions of the FPGA, flash, regulator topology, or connectors.
  • Include assembly notes for BGA moisture handling, stencil, thermal profile, and inspection.
Firmware-Relevant Hardware Requirements
Host firmware must implement USB transport, register transactions, package staging/verification, configuration writes/readback, tick sequencing, gate/unload/restore experiments, microSD access, logging, status LEDs, and fault reporting.
FPGA integration firmware/RTL must add a thin SPI bridge wrapper around bind_fabric_8c while preserving every existing port semantic.
Physical Design Expectations
  • Prioritize accessible connectors and test points over minimum board area.
  • Keep USB, JTAG, microSD, power input, and raw debug connectors at board edges.
  • Reserve top-side space above the FPGA for a heat spreader or small heatsink.
  • Add mounting holes and unobstructed probe access.
Important Design Decisions
  1. Preserve BIND_8C semantics and add only a transport wrapper.
  2. Use SPI between host MCU and FPGA rather than a direct 124-bit MCU bus.
  3. Use microSD for prototype storage; treat 50 TB as a future system-level target.
  4. Use Master SPI boot with independent JTAG.
  5. Use a 25 MHz oscillator for the first board.
  6. Use 3.3 V general-purpose I/O banks initially.
  7. Recommend an 8-layer PCB for first-spin risk reduction.
  8. Re-P&R after the final physical pin map; do not use the supplied .bin as the board image.
Assumptions and Unresolved Decisions
  • Exact USB MCU and regulator MPNs are not yet selected.
  • Exact SPI flash capacity/MPN and microSD connector are not yet selected.
  • Exact CABGA381 ball map and bank allocation await official pinout ingestion.
  • Final power budget and thermal solution await a constrained implementation and Lattice power estimate.
  • The SPI wrapper protocol and RTL are integration deliverables not present in the pack.
  • Input power sufficiency from a single USB-C source remains to be proven by the final budget.
  • Full raw-bus connector retention versus reduced validation connectors remains a mechanical/cost decision.
Success Criteria
  1. All rails meet tolerance and sequencing requirements.
  2. JTAG identifies the exact FPGA.
  3. Board-specific image configures SRAM and boots from SPI flash.
  4. n_clusters_ro reads 8.
  5. Known config writes/readbacks succeed for all clusters.
  6. Sensor input, tick, done, effort, and gate behavior are observable.
  7. Host loader/storage experiments execute and log reproducibly.
  8. No claim of physical validation is made until assembled hardware is tested.
Change Notes
  • Initial specification created from the user brief and supplied BIND_8C source pack.
  • Corrected the measured final routed Fmax to 62.91 MHz.
  • Recorded the absence of physical pin constraints and the requirement to re-P&R.
  • Selected the preliminary USB-MCU/SPI-wrapper/microSD architecture.