SUPERSEDED — HISTORICAL 11-AIRWIRE STATE; NOT CURRENT BUILD OR FITTING INSTRUCTIONS. This file records the 21 September 2026 intermediate 12→11 airwire reset ECO only. Current CAD audit reports 0 airwires and 0 redundant traces and the manual-wire scope is 15 links, not just R70. The historical airwire list and instructions below must not be used as an assembly order, current routing status, wire traveler, or manufacturing-release authority. Use the revision-specific Fabricator Assembly Handoff and Board Bring-Up Plan; all their shop-access, landing, procurement and test holds apply. No physical fit or release is established by this old CAD snapshot.
Retained result — 2026-09-21
Completed: 12 → 11 live PCB airwires. Stopped after this first retained reduction. Baseline checkpoint: #07df922c; retained copper checkpoint: #186dc223.
This is an assembly-wire ECO, not a claim that continuous board copper now crosses the former reset gap. R70 must be fitted as insulated wire between TP34 and TP35 during assembly. The board as a whole remains incomplete and is not fabrication-ready.
Exactly what changed
Added TP34 and TP35, reusing the exact live-project BIND_WIRE_LAND_SMD_V2 part/version used by TP33. Library searches did not find the private/custom land, but the existing project part was successfully reused and its new instances inspected.
TP34: Top, center (-9.0, 29.6) mm, on the existing D3-anode-to-J5:6 copper. Approximately 2.263 mm of existing 0.20 mm Top copper connects D3:A at (-10.6, 28.0) to this land. No new long lead or via was added at this endpoint.
TP35: Top, center (20.5, 6.0) mm, next to R25:P2. Added two 0.15 mm Top segments: (20.885770772262497, 3.9767677083859496) → (20.5, 4.362538480648447) → (20.5, 6.0) mm. Total centerline length approximately 2.183 mm.
Added R70, a schematic-only 0 Ω fitted-wire representation, excluded from PCB and pick-and-place. R70 remains in the BOM as the mandatory hand-install operation; do not populate an SMT 0402 resistor for R70. Its Package field is only inherited schematic/generic-part metadata, not an assembly footprint.
The two land-only components are excluded from BOM and pick-and-place; their copper is fabricated with the PCB.
Split D3:A and J5:6 into FPGA_RST_N_MANUAL, with TP34 and R70:P1.
Retained FPGA_RST_N for U1:PT58B, R14:P1, R25:P2, TP35 and R70:P2.
Migrated the seven existing D3-to-J5:6 Top segments to FPGA_RST_N_MANUAL by exact-geometry recreation. Their widths and coordinates were preserved. All other existing copper and all original component placements were untouched.
No autorouter, pathfinder attempt, neighboring-net rip-up, new via, pin remap, or original-component move was performed.
Why this bounded path
Read the routing handoff and inspected live geometry before editing. The FPGA-side reset island has a congested escape around R14: nearby 3V3 fanout, 2V5 copper and Host-SPI routing leave no proven direct corridor to the D3/J5 island without disturbing validated copper. The existing R25:P2 endpoint of that same island provides space for a short local land connection instead. The ECO bridges only this low-speed reset gap; it does not apply to power, CCLK, PROGRAMN or DONE.
The pre-routing board check reported the existing 2V5/VCCAUX_F15 track-width warning and an EP via-at-SMD information item. These are unrelated to the selected reset ECO and were left untouched. No routing job was launched.
Mandatory assembly instruction
Locate Top-side TP34 near D3 and TP35 north of R25:P2 using the coordinates above.
Fit one insulated fine-gauge copper wire (for example 30 AWG) between the two lands to implement R70. Straight endpoint separation is approximately 37.8 mm; cut to the actual dressed path with strain-relief allowance, not to this straight-line distance.
Keep insulation intact between the solder joints. Strip only enough for each land; do not bridge nearby exposed copper. Do not solder onto a BGA pad or via.
Dry-fit a path clear of connector access, reset switches, hot parts and sharp edges. Keep it close to the board, avoid long parallel runs beside clocks/USB/Host-SPI, and secure the insulation with suitable assembly strain relief. Keep both land joints inspectable.
Inspect solder joints under magnification. With power removed, verify TP34↔TP35 continuity (target <1 Ω including probe resistance after subtracting lead resistance), and verify no unintended short to adjacent ground/power copper.
During eventual board bring-up, verify manual reset at D3/J5 propagates to FPGA_RST_N/U1:PT58B and that releasing reset restores the pulled-up level. The separate FPGA_RST_N_MCU PCB airwire is still unresolved; do not mistake this ECO for completing the MCU reset connection.
No firmware or FPGA pin-map change is required by this ECO. Assembly/bench functional validation remains unattempted; the results below are CAD verification only.
Verification and acceptance gate
Fresh routing_state and get_checks after the retained copper edit:
Placement tool also reported zero remaining overlaps, keepout violations and out-of-bounds components. Read-back confirms TP34/TP35 positions and R70 absent from the PCB, with Exclude from PCB and Exclude from Pick & Place both true. Schematic inspection confirms both exact net memberships above. Only the 11 known airwire errors remain among the requested gate checks. The temporary net-ownership overlap during migration was resolved before retention.
USB_VBUS_SENSE remains closed. Validated USB/Host-SPI copper and FPGA SCK on PR89A were not edited. Existing R25/R63/U2 placement was preserved.
Completed: one bounded low-speed assembly-wire ECO, schematic split/fitted link, both local solder lands and local copper, acceptance-gate verification, assembly documentation.
Unattempted by design: second reduction, full-board routing, alternative direct-copper path, physical assembly and bench validation.
Failed items: none retained. No rollback required; the acceptance gate passed.