This plan applies to the final verified CAD revision: 0 airwires, 0 redundant traces, no open blocking DRC findings, and 0 missing-MPN findings. The U6 VIN/SW clearance and U6/L2 power-stage checks pass in the live project. Use only the latest regenerated Gerber, BOM, pick-and-place, and IPC-D-356 files; earlier exports are obsolete. Supplier acceptance of the three 0.45/0.20 mm vias and Type VII capped PROGRAMN via-in-pad remains required before manufacture.

Use the Fabricator Assembly Handoff current traveler as the controlling 15-link list: R26 TP5–TP9, R34 TP11–TP14, R35 TP25–TP26, R38 TP27–TP28, R65 TP29–TP26, R66 TP30–TP26, R67 TP31–TP28 (PA15/38), R68 TP32–TP28, R69 TP33–TP15 (PB4/40), R70 TP34–TP35, R71 U2 PA13/34–J4:2, R72 U2 PB1/19–R25:P1, R73 TP17–TP19, R74 TP27–TP22, R75 TP21–TP20. 0 CAD airwires/0 redundant traces is not a passed assembly test. The earlier Reset Wire ECO describes a historical 11-airwire intermediate state and is not a current fitting authority.

Order and pre-power HOLD: Obtain written shop signoff or redesign larger lands for the three wires each at TP26 and TP28 and two at TP27, each 0.7 × 0.9 mm; no qualified multiwire fitting process is assumed. U2 is UFQFPN: exposed solderable PA13 and PB1 leads after population are unverified, not gull-wing leads; R71/R72 cannot be fitted until a verified accessible landing and method are approved or redesigned. R25 is an unapproved-MPN axial jumper whose P1 is R72's proposed joint; confirm actual procurement, fit and solderability. TP15 (21.25, −30.77 mm) is a 4.7 × 3.43 mm same-net top-copper landing for R69 but its 5018 footprint has Exclude from BOM=true; determine whether a part is fitted or it is bare, mask opening, joint access and strain relief, and retain MISO probe access. J5:9 routing also uses Mid-Layer 5; do not assume a top-only physical path. Confirm all other populated access, paths, insulation, edge clearances and testpoint probe availability. No wire-fit authorization, procurement release or power-up is implied here.

Sequence, recorded against the actual PCB/assembly revision and serial: first inspect and electrically test the bare board against revision-matched copper/netlist for expected copper continuity and adjacent-net isolation (not across absent fitted wires); then document physical population and gain shop approval for all proposed landings and dressing. After controlled fitting, check all 15 installed bridges unpowered for continuity to the correct intended net and adjacent-net/rail isolation; magnify joints, confirm strain relief and intact probe access, photograph and sign off each. Count 30 manual terminations at 25 distinct sites, plus R25's joints. Failure or missing fit evidence blocks step 1 and all powered tests; repair and retest the affected earlier gates. Netlist describes intended connection, PnP describes automatic placements, and only the manual traveler verifies fitted wires. No physical test pass is claimed.

Scope: First professionally assembled, eight-layer BIND 8C validation PCBA. This is a bench procedure and blank record, not a claim that the board has been assembled or tested. At document creation, live CAD routing reports 0 airwires and 0 redundant traces. A CAD connection, even one represented by a schematic-only fitted wire, is not proof of continuity on an assembled board. Stop on a failed gate; record repair and repeat the affected earlier tests before continuing. Use ESD protection, magnification, a calibrated DMM, current-limited bench supply, oscilloscope with short ground lead, and correctly keyed/debugger-compatible cables. Keep USB host and AUX supply disconnected until the relevant step.

Record PCB revision/serial, BOM and assembly revision, fabrication lot, via-in-pad process approval, ECO wire-fit list, image and firmware hashes/versions, equipment IDs, operator, date, temperature and supply configuration. Confirm U1 LFE5U-85F-6BG381C orientation/marking, U2 STM32F411CEU6, U3 W25Q128JVSIQ, J1 USB-C, J2 microSD, J3 FPGA JTAG, J4 MCU SWD, J6 AUX 5 V, Y1 25 MHz oscillator, power U8/U7/U4/U5/U6, polarity and connector pin-1 orientation against as-built data. Inspect both faces for damaged parts, wrong population, solder bridges, exposed or moving ECO conductors and inaccessible test pads. Require first-article X-ray of all U1 BGA rows/balls for bridges, opens/voids, registration and via-in-pad assembly defects, with inspected images and acceptance disposition logged; a visual top-side glance is not sufficient. Do not attach USB and AUX simultaneously during initial tests; U8 is the dual-source mux, not proof that either input behaves correctly.

Mandatory fitted insulated-wire ECO inventory, live schematic roles: R65–R75 are schematic 0 Ω wire representations excluded from PCB/pick-and-place, not SMT resistors. Confirm each actual insulated bridge, local land solder joint, strain relief, routing away from BGA/clock/USB, and absence of neighboring copper shorts. With all power removed, null DMM leads, check each endpoint pair for low continuity and adjacent-net isolation; record measured resistance and neighbor nets, use the assembly drawing for safe accessible probe sites. Never infer a bridge is fitted from an electrical CAD net alone.

Any unconfirmed bridge landing, missing fit, continuity open, solder bridge or adjacent short is a hold, not a documentation pass. Before wire-fit, request a top-side assembly drawing and shop review of all 15 manual links R26/R34/R35/R38/R65–R75: small 0.70 × 0.90 mm wire lands (TP9 reserved only for R26), TP15's larger 5018 termination for R69, pad/mask accessibility after population, edge clearance at TP32 (10.16,48.50 mm), insulated-wire path and strain relief. For R71/R72, U2 PA13/PB1 are UFQFPN pins without verified exposed solderable leads after population: do not attempt direct lead soldering absent an approved shop finding or redesign. Confirm J4:2 and R25:P1 actual solderable access separately. R70 follows the current assembly traveler; the separate reset ECO is historical. R73–R75's larger test points still require mechanical fit and FPGA remap approval.

R69 landing: R69's Role Details now identifies fitted TP33 (U2:PB4) → TP15 (HOST_SPI_MISO); TP9 remains R26-only. The physical fit gate remains: check whether TP15's 5018 is populated and presents accessible solderable metal or whether its bare copper pad is available, preserve probe access, approve dressed top-side wire clearance, then inspect and test the actual wire before the Host SPI step. Never double-fit TP9.

DMM resistance/diode checks, supply and storage disconnected: TP24 (GND) or J4:3/5 to TP1 (USB_VBUS), J6 AUX pins to GND, TP2 (5V_MAIN) to GND, TP3 (3V3) to GND, TP6 (2V5) to GND, TP7 (1V1) to GND. Also check each distinct rail against each other, U3 VCC/GND and J2:VDD (pin 4)/VSS (pin 6), and verify no unintended external source backfeed. Capacitors may charge during resistance measurement; log stabilized readings, polarity and settling, compare with same-revision known-good reference and calculated expected loads. No universal resistance threshold is asserted here. Hard/steady low resistance, a rail-to-rail short, reversed polarity or unexplained asymmetry is a fail requiring isolation and reinspection before power. Verify ECO endpoints only connect their intended nets, not nearby 3V3/GND/other signals.

Prefer J6 AUX input (AUX_5V_IN at J6 pins 1/3/5/7/9 and GND at 2/4/6/8/10; verify header orientation on physical board) from a bench supply with USB J1 disconnected. Before attaching the board, characterize supply leads and check output polarity; start with supply output off, set nominal input from the documented AUX design and a conservative current limit chosen from measured cold resistance/observed ramp current, component/input-source ratings and a defensible startup load estimate, not a guessed fixed ampere value. Raise the limit only after checking actual rail loads and protection-device ratings; if the supply enters current limit, shut down and diagnose, do not simply turn up the limit. Record supply setpoint, limit, input voltage/current and inrush/steady current. Do not assume a regulator enable order or FPGA-required sequencing from this document; record observed rise order and verify against current component datasheets and actual board constraints before declaring it acceptable.

One-by-one measurement means probe and log each rail individually through startup and steady state, not assert unverified independent switching or power sequencing. Capture power-on waveforms versus GND with rated high-impedance probes, watch for unexpected overshoot, brownout and localized heat. Stop and remove power for any short, excessive current, missing rail or unexpected PG. After AUX passes, power down and separately test USB-C J1 with a safe host/source: TP1 → TP2 path, CC orientation, no backfeed into J6, and measured source-advertisement/current sufficiency under expected load; USB-C is not automatically a 3 A source.

With stable rails, use J4:1 3V3 reference and J4:3/5 GND, J4:2 SWDIO (via R71 from U2:PA13), J4:4 SWCLK (U2:PA14), J4:10 NRST if used (verify actual physical keyed pinout). Attach an appropriate 3.3 V reference-sensing SWD probe; connect without powering the target through the probe unless explicitly engineered. Read STM32 device identity and read-only memory safely, verify reset/attach and that MCU_NRST behaves; do not mass-erase or program before archiving factory/board contents and approving firmware. SWDIO failure first gates inspection of R71 and adjacent shorts. Log reported ID, probe voltage and connection outcome; pass is reproducible correct identity and stable attach, not a guessed numeric ID.

Use J3:1 3V3 reference, J3 ground pins as verified on the board, J3:2/4/6/8 corresponding to TMS/TCK/TDO/TDI header nets via board series paths to U1 TMS/TCK/TDO/TDI. Confirm cable pinout, reference voltage and no short on those four lines. Scan JTAG read-only, capture full device identification and compare with manufacturer's exact fitted FPGA/device-code documentation; repeat after reset. Pass is stable ID and chain access without driving unintended voltages. Failure is not masked by a CAD-only zero-airwire result.

Probe TP8 FPGA_CLK_25M → U1:PT63A/A10 against TP24 GND with Y1:OUT on FPGA_CLK_SRC feeding the clock path. Expect a stable 25 MHz clock only after Y1 power/enable and board path are confirmed; verify frequency, logic amplitude, duty/rise and absence of clock loading against Y1 and U1 input limits. Record measured values; do not short or overdrive the clock node.

Before any image operation record U3 3V3, FPGA_CFG_CS_N (U3 pin 1), FPGA_CFG_SCK (U3 pin 6; TP10), FPGA_CFG_MOSI (U3 pin 5), FPGA_CFG_MISO (U3 pin 2), FPGA_CCLK_RAW (U1 CCLK), FPGA_PROGRAMN (U1 PROGRAMN, also J3 and J5), FPGA_INITN (U1 INITN; TP12/J5), and FPGA_DONE (U1 DONE; TP18/J5). Verify static idle levels against actual pull network and mode straps; capture PROGRAMN assertion/release and INITN/DONE response on reset. No assertion polarity/timing window is invented: compare transitions against Lattice and flash documentation. Hold on any stuck-low, rail violation or unstable configuration path.

Verify U3 identification via an approved non-destructive flash read, record JEDEC ID and pre-existing image/hash. Only after exact board-revision pin mapping, wrapper remaps (R73–R75), fit state, timing/build logs, image hash and flash programming method are confirmed, load the matching board-specific FPGA image (JTAG SRAM first if practical), verify INITN/DONE and JTAG access, then program and verify flash only with approved contents and backup. Cold-cycle and check autonomous boot separately. Pass: correct device ID and image hash, reproducible DONE/config success and functional board-specific readback; DONE alone does not validate fabric. Legacy unconstrained BIND_8C_ECP5_85.bin is explicitly barred.

Gate all of these on stable power, fitted wires, accessible SWD/JTAG, approved MCU firmware and approved board-specific FPGA image. USB: connect J1 as USB 2.0 device (U2:PA11 USB_D_N, PA12 USB_D_P, PA9 USB_VBUS_SENSE), test both Type-C orientations, enumerate with expected approved VID/PID/descriptors, measure bus/current, transfer/reconnect/error behavior, no backfeed. Log host OS and observed descriptors rather than assuming IDs. microSD: J2 pin 4 3V3, pin 6 GND; MCU SPI U2:PB12 SD_CS_N→J2 CD/DAT3 pin 2, PB13 SD_SCK→J2 CLK pin 5, PB14 SD_MISO←J2 DAT0 pin 7, MOSI→J2 CMD pin 3; U2:PB5 SD_CARD_DETECT→J2 pin 10. With approved sacrificial card, confirm detect insertion/removal, initialize, write/read/compare known test data and safe reinsert; protect user media.

Host SPI: validate MCU-to-FPGA clock, CS, MOSI, MISO and IRQ at actual TP13 HOST_SPI_SCK, TP15 HOST_SPI_MISO, TP16 HOST_SPI_CS_N, TP17 HOST_SPI_IRQ, and the relevant fitted-land bridges. Confirm live U2:PA5 SCK, PA15 CS, PB4 MISO, PA7 MOSI, PB0 IRQ and U1 locked pin map against the actual new image before driving. The TP31/TP33 PA4/PA6 wording was stale property text, now corrected; do not recast it as evidence of a changed circuit. Confirm the new R69 TP33→TP15 fit, PB4→TP15 continuity and TP15→TP9/J5:9 continuity before this test; retain TP15 probe access.

Only then run BIND functional acceptance with a documented stimulus and golden result for the actual wrapper: read MAGIC = 0xB1D8 only if that register is implemented by the approved image; check n_clusters_ro = 8; perform known configuration write/readback for all eight clusters, input sensor A/B, tick, done, effort and gate/unload/restore cases without changing the locked fabric semantics. Log firmware/image hashes, stimulus, measured results and mismatch traces. TP19 (DBG_TICK_START) and TP20 (DBG_TICK_DONE) reflect remapped nets on this ECO board, so they are not independent evidence of original tick behavior; validate through the registered interface and constrained-image documentation instead. Never substitute simulation or RTL build results for on-board evidence.

Final disposition: PCBA process release: ___ / held by ___; powered rail check: ___; SWD identity: ___; FPGA JTAG/config: ___; USB/SD/host SPI: ___; BIND functional validation: ___; known deviations and approvals: ___; repeat-test evidence: ___. A physically validated prototype requires actual instrumented pass records, approved image and firmware, no unresolved safety/assembly failures, and sign-off; unrun or blocked tests are not passes.

Known blockers: no physical measurements, X-ray report or wire-continuity records supplied. Hard order holds remain for shared-land shop signoff or larger-land redesign (TP26/TP28/TP27), U2 UFQFPN PA13/PB1 solderable access or redesign, R25 MPN and actual joint/fit, TP15 fitted-5018-versus-bare-pad mask/solderability/probe-access disposition, 19 missing physical MPNs, and all other as-built wire access and strain relief. No double-wire TP9 fit is authorized. Rail tolerances, current limit, PG logic/timing and complete sequencing have not been substantiated with as-built component ratings and measured load; approved MCU firmware and retrievable verified board-specific image/protocol are not established; manufacturing approval of 0.45/0.20 mm overrides is required. Resolve each gate before claiming a pass.