Fresh live validation reports 0 airwires, 0 redundant traces, no blocking copper/layer/placement/stackup findings, no U6/L2 power-stage or pad-clearance findings, and 0 missing-MPN findings. The U6 5V_MAIN-to-SW clearance is 0.100 mm, exceeding the configured 0.0889 mm minimum. Manufacturing exports generated before this final state are obsolete and must not be ordered.
The remaining supplier gate is process capability: written acceptance of the three local 0.45 mm pad / 0.20 mm drill through-vias, including the PROGRAMN IPC-4761 Type VII resin-filled, planarized, copper-capped via-in-pad construction. Supplier CAM review may propose tolerances or stackup adjustments, but no geometry or process substitution is authorized without design review.
Controlled via-in-pad process
The board uses IPC-4761 Type VII VIPPO for every drilled through-via whose hole or annular ring overlaps a component pad.
Required process:
Via construction: plated through-hole, nominal 0.30 mm finished hole / 0.60 mm pad.
Fill: nonconductive epoxy/resin, fully filled with no exposed void at the pad surface.
Finish: planarized and copper plated over/capped on both outer surfaces before final surface finish.
Via-in-pad locations must not be supplied as open, tented, or merely plugged vias.
Fabricator must perform registration and annular-ring review for the 0.80 mm-pitch CABGA381 footprint before acceptance.
Any proposed change to drill, capture-pad diameter, finished board thickness, or layer registration must be approved before fabrication.
Electrical test must include the production netlist; X-ray inspection of the FPGA BGA is required for first-article assembly.
Design interpretation
The Controlled VIPPO Through-Vias PCB ruleset permits the existing stackup's Through-hole via option to overlap pads. This is a manufacturing-process authorization, not permission for arbitrary overlapping copper or different-net clearance violations.
The existing eight-layer stackup and routing are unchanged. New FPGA power escapes may use the same controlled VIPPO construction, subject to focused DRC after each connection.
Ordering gate
Do not release the board to a standard low-cost process that cannot explicitly confirm filled, planarized, copper-capped via-in-pad. The fabrication quote and order notes must state IPC-4761 Type VII / VIPPO and identify the nominal 0.30/0.60 mm via geometry.
Additional local via geometry — routing completion 24 September 2026
The FPGA configuration finish added three local 0.20 mm drill / 0.45 mm copper-pad through-vias, overriding the stackup's nominal 0.30/0.60 mm via option: one capped VIPPO centered on U1:PROGRAMN at (-11.000,-6.800) mm; one DONE escape at (-11.000,-8.900) mm; and one DONE transition at (-6.500,-9.900) mm. The project DRC reports zero errors and zero airwires, but that is not confirmation the fabricator supports the new via geometry. Obtain explicit written approval for the 0.20 mm drill, 0.45 mm annular land, registration, aspect ratio, and Type VII copper-capped via-in-pad process before issuing production Gerbers. If the fabricator cannot support them, these overrides must not be released as-is. See Routing Completion.
Final CAD release state — 24 September 2026
Controlled via-in-pad process
Design interpretation
Ordering gate
Additional local via geometry — routing completion 24 September 2026