Routed J1/J2 through AC-coupling and RF filters into SW1, and from SW1 into U1/U4 preamp +IN pins; unused inputs tied off.
Fanned out 1.65 V bias from U5 to BIAS_NET; wired VR1 wipers into the U1 feedback loops.
Added seven 100 nF decoupling capacitors (C1–C7) to power pins of U1, U4, U2, U3, and U5, with returns to ground.
Remaining tasks
Implement master volume (VR2) and design selectable 40/80 kHz RC filters; connect to U3 inputs.
Finalize 3.3 V buffers in U3 with series resistors, D2/D3 Schottkys, U6/U7 TVS, and F1/F2 PTCs.
Prepare schematic for 2-layer PCB: annotate star ground, add routing guidelines, run ERC to clear any airwires.
Success criteria status
Nets routed with no airwires: ✅
Combo jack to mode switch to preamps: ✅
1.65 V bias and VR1 gain control: ✅
Master volume and anti-alias filters: ❌
U3 buffers with MCU protection: ❌
PCB-ready with star ground: ❌
Recommended next step
Proceed to implement the master volume stage and anti-alias filter networks (Plan step 3) to complete the signal path before moving on to MCU protection and PCB layout preparation.
Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power