Audio Signal Conditioning Circuit

flux

Work completed
  • Routed J1/J2 through AC-coupling and RF filters into SW1, and from SW1 into U1/U4 preamp +IN pins; unused inputs tied off.
  • Fanned out 1.65 V bias from U5 to BIAS_NET; wired VR1 wipers into the U1 feedback loops.
  • Added seven 100 nF decoupling capacitors (C1–C7) to power pins of U1, U4, U2, U3, and U5, with returns to ground.
Remaining tasks
  • Implement master volume (VR2) and design selectable 40/80 kHz RC filters; connect to U3 inputs.
  • Finalize 3.3 V buffers in U3 with series resistors, D2/D3 Schottkys, U6/U7 TVS, and F1/F2 PTCs.
  • Prepare schematic for 2-layer PCB: annotate star ground, add routing guidelines, run ERC to clear any airwires.
Success criteria status
  • Nets routed with no airwires: ✅
  • Combo jack to mode switch to preamps: ✅
  • 1.65 V bias and VR1 gain control: ✅
  • Master volume and anti-alias filters: ❌
  • U3 buffers with MCU protection: ❌
  • PCB-ready with star ground: ❌
Recommended next step Proceed to implement the master volume stage and anti-alias filter networks (Plan step 3) to complete the signal path before moving on to MCU protection and PCB layout preparation.

Flux stopped

J1
D1
L6
Inductance
100 nH
C4
Capacitance
100 nF
J2
C6
Capacitance
220 nF
C11
Capacitance
390 pF
U6
C8
Capacitance
820 pF
C7
Capacitance
220 nF
U7
L3
Inductance
100 nH
C9
Capacitance
820 pF
L4
Inductance
100 nH
D4
C2
Capacitance
100 nF
L1
Inductance
100 nH
L5
Inductance
100 nH
C10
Capacitance
390 pF
C3
Capacitance
100 nF
C1
Capacitance
100 nF
C5
Capacitance
100 nF
L2
Inductance
100 nH
Hole1
Hole4
TP1
TP2
U5
U1
TP2
Hole2
SW1
D2
Hole3
TP3
F1
TP1
VR1
TP3
D3
U4
VR2
F2
U2
U3

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Documents

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    Assets

    Assets are files uploaded to this project which can be used in various ways.

    Audio Input for 3.3v ADC thumbnail
    Stereo Balanced Audio Front-End for Daisy Seed 2 DFM Platform

    Properties

    Diagram
    


  
    
  
  
    
  



""Input Stage""


""Bias & Mid-Rail Distribution""


""Variable Gain Stage""


""Master Volume""


""Anti-Alias Filters""


""Output Buffers""


""MCU Protection & Outputs""


""Power & Decoupling""






































































AC Coupling

AC Coupling

AC Coupling

AC Coupling

AC Coupling

AC Coupling

Biasing

Biasing






























































"Balanced Mic In L (J1)"
"RF/EMI Filter L"
"Mic Preamp L (U1)"
"Instrument In L (J1)"
"RF/EMI Filter L"
"Hi-Z Buffer L (U4)"
"Line In L (J1)"
"RF/EMI Filter L"
"Line Attenuator L"
"Balanced Mic In R (J2)"
"RF/EMI Filter R"
"Mic Preamp R (U1)"
"Instrument In R (J2)"
"RF/EMI Filter R"
"Hi-Z Buffer R (U4)"
"Line In R (J2)"
"RF/EMI Filter R"
"Line Attenuator R"
"Mode Switch SW1 (MIC / INST / LINE)"
"ESD / TVS Protection D1 + TVS"
"1.65V Ref Source"
"U5 OPA188 Buffer"
"1.65V Mid-Rail (BIAS_NET)"
"Preamp Bias Nodes U1/U4"
"Post-Gain Bias Nodes"
"GAIN_A (VR1 Ch1)"
"GAIN_B (VR1 Ch2)"
"VR1 Dual Pot (Preamp Gain)"
"FB_A / FB_B Feedback Nets"
"Post-Gain L"
"VR2 Ch1"
"Post-Gain R"
"VR2 Ch2"
"Volume Controlled Outputs L/R"
"Vol Out L"
"AA RC node_40kHz L"
"AA RC node_80kHz L"
"Vol Out R"
"AA RC node_40kHz R"
"AA RC node_80kHz R"
"AA Filter Select"
"Selected AA Out L"
"U3 Buffer A (3.3V)"
"Selected AA Out R"
"U3 Buffer B (3.3V)"
"Series R + PTC F1 L"
"Schottky Clamp D2 L"
"TVS to 3.3V/GND"
"Daisy ADC D1"
"Series R + PTC F2 R"
"Schottky Clamp D3 R"
"TVS to 3.3V/GND"
"Daisy ADC D2"
"TP1/TP2/TP3 Test Points"
"3.3V Rail"
U3
U2
U5
"12V Rail"
U1
U4
"C1-C7 Local Decoupling"

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    Controls