I’ll replace the inherited MAX3232 footprint/model references with a W25Q02JVSFIM-specific SOIC-16 wide-body footprint/model asset, then verify the layout metadata no longer points to MAX3232.
Replaced the footprint and 3D model rule references with W25Q02JVSFIM-specific SOIC-16W assets and removed the old MAX3232 footprint/model assets. I updated the report here: W25Q02JVSFIM Part Review.
Open items:
The layout rule references are corrected, but the inspector still shows cached/generated MAX3232 payload details inside the rendered geometry; a layout refresh/rebuild may be needed to fully regenerate the geometry text.
Suggested next steps:
Refresh/rebuild the footprint geometry from the new W25Q02JVSFIM asset.
Re-check the part before publishing.
Fix the remaining pins 12–14 N/C display labels if strict naming consistency is required.
Official family: Winbond W25Q02JV / W25Q-JV QSPI NOR family
Existing project metadata
Part Type: Integrated Circuit
Manufacturer Part Number: W25Q02JVSFIM
Manufacturer Name: Winbond Electronics
Package or Case Code: 16-SOIC
Designator Prefix: IC
Symbol Style: parametric-v1
Components in symbol: 16 terminal objects
Nets: 0
BOM items: 0
Key specifications
Memory density: 2 Gbit Serial NOR Flash
Organization: 256M x 8
Supply voltage: 2.7 V to 3.6 V
Interface modes: Standard SPI, Dual SPI, Quad SPI, QPI, DTR
Clock rate: up to 133 MHz STR; W25Q02JV_DTR family supports DTR operation
Operating temperature: industrial range, typically -40 °C to +85 °C for this ordering class
Package for W25Q02JVSFIM: 16-pin SOIC, 7.50 mm wide-body class
Symbol update status
Updated the functional terminal labels and pin metadata to align with the datasheet:
Table
Pin
Expected function
Current symbol label
Pin type
Description status
1
/HOLD or IO3
/HOLD (IO3)
Bi-Directional
Added
2
VCC
VCC
Power In
Added
3
/RESET
/RESET
Input
Added
4
NC
NC
Not Connected
Added
5
NC
NC
Not Connected
Added
6
DNU
DNU
Reserved
Added
7
/CS
/CS
Input
Added
8
DO or IO1
DO (IO1)
Bi-Directional
Added
9
/WP or IO2
/WP (IO2)
Bi-Directional
Added
10
GND
GND
Ground
Added
11
DNU
DNU
Reserved
Added
12
NC
N/C
Passive
Added
13
NC
N/C
Passive
Added
14
NC
N/C
Passive
Added
15
DI or IO0
DI (IO0)
Bi-Directional
Added
16
CLK
CLK
Input
Added
Notes on NC naming
Pins 4 and 5 are normalized as NC.
Pins 12, 13, and 14 still display as N/C in the current symbol/footprint despite rename attempts using the unique terminal identifiers. Their descriptions are correct, but the label rename did not persist through the available editor operation.
Recommended follow-up if publishing: manually rename pins 12-14 in the terminal editor, or rebuild those terminals so all no-connect labels display as NC consistently.
SOIC-16 footprint land-pattern audit
The footprint payload currently identifies itself as:
SOIC-16_L10.3-W7.5-P1.27-LS10.3-BL
Source asset/model path still references MAX3232ECWE+T
Extracted land pattern from footprint payload:
Pin count: 16 SMD pads
Pin pitch: 1.27 mm
Pad size: 0.57 mm x 2.40 mm, oval SMD pads
Pad row center-to-center spacing: 9.50 mm
Approximate toe-to-toe span: 11.90 mm across pad length direction
Pad columns span: about 8.89 mm from pin 1 to pin 8 centers
Silkscreen body outline: about 10.46 mm x 6.64 mm
Footprint assessment
The geometry is broadly consistent with a wide-body SOIC-16 footprint for a 10.3 mm lead-span / 7.5 mm body-width package class.
The pad pitch and 16-pin numbering pattern are correct for the W25Q02JVSFIM 16-SOIC package.
The footprint source asset and 3D model are mismatched: they reference MAX3232ECWE+T, not W25Q02JVSFIM/Winbond. This is acceptable only if the mechanical package is identical, but it is a publishing-quality metadata issue.
The footprint is marked through-hole in the imported KiCad module attributes even though the pads are SMD. Pads themselves are SMD, so fabrication geometry is usable, but the module attribute should be cleaned if possible.
Remaining mismatches / recommendations
Normalize pins 12-14 display labels from N/C to NC; the attempted batch rename did not persist.
Verify the Winbond package drawing tolerances against the 0.57 mm x 2.40 mm pad geometry before publishing; current geometry appears reasonable for SOIC-16 wide-body but was not confirmed from the package drawing dimensions inside Flux.
If available, set the native project Datasheet URL property directly; the URL is present in project metadata/history but the datasheet query service previously did not recognize it.
Footprint / 3D model replacement update
Replaced the inherited MAX3232 footprint/model asset references with W25Q02JVSFIM-specific SOIC-16W assets:
Default 3D model asset: W25Q02JVSFIM_SOIC-16W_7.5x10.3mm_P1.27mm.step
Source: KiCad Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm and matching KiCad STEP model, matching the W25Q02JVSFIM 16-SOIC / SOIC-W / 300 mil package class.
Removed the previous MAX3232 footprint and model assets from the project asset list.
Verification note: the active layout rules now reference the W25Q02JVSFIM assets. The layout inspector still shows the previous MAX3232 payload/model path inside cached/generated geometry details, so the rule-level asset reference is corrected but the rendered geometry may need a refresh/rebuild cycle to fully regenerate from the new asset payload.