Building Linux SBC Around STM32 Chip
Thought for 3 mins 28 sec
Here is the complete 12-column grid (including NB entries) for K4F6E3S4HM-MGCJ, rows A–AB and columns 1–12.
Csv
Row,Col,Signal A,1,DNU A,2,DNU A,3,VSS A,4,VDD2 A,5,ZQ A,6,NB A,7,NB A,8,NC A,9,VDD2 A,10,VSS A,11,DNU A,12,DNU B,1,DNU B,2,DQ0_a B,3,VDDQ B,4,DQ7_a B,5,VDDQ B,6,NB B,7,NB B,8,VDDQ B,9,DQ15_a B,10,VDDQ B,11,DQ8_a B,12,DNU C,1,VSS C,2,DQ1_a C,3,DMI0_a C,4,DQ6_a C,5,VSS C,6,NB C,7,NB C,8,VSS C,9,DQ14_a C,10,DMI1_a C,11,DQ9_a C,12,VSS D,1,VDDQ D,2,VSS D,3,DQS0_t_a D,4,VSS D,5,VDDQ D,6,NB D,7,NB D,8,VDDQ D,9,VSS D,10,DQS1_t_a D,11,VSS D,12,VDDQ E,1,VSS E,2,DQ2_a E,3,DQS0_c_a E,4,DQ5_a E,5,VSS E,6,NB E,7,NB E,8,VSS E,9,DQ13_a E,10,DQS1_c_a E,11,DQ10_a E,12,VSS F,1,VDD1 F,2,DQ3_a F,3,VDDQ F,4,DQ4_a F,5,VDD2 F,6,NB F,7,NB F,8,VDD2 F,9,DQ12_a F,10,VDDQ F,11,DQ11_a F,12,VDD1 G,1,VSS G,2,ODT_CA_a G,3,VSS G,4,VDD1 G,5,VSS G,6,NB G,7,NB G,8,VSS G,9,VDD1 G,10,VSS G,11,DNU G,12,VSS H,1,VDD2 H,2,CA0_a H,3,NC H,4,CS_a H,5,VDD2 H,6,NB H,7,NB H,8,VDD2 H,9,CA2_a H,10,CA3_a H,11,CA4_a H,12,VDD2 J,1,VSS J,2,CA1_a J,3,VSS J,4,CKE_a J,5,NC J,6,NB J,7,NB J,8,CK_t_a J,9,CK_c_a J,10,VSS J,11,CA5_a J,12,VSS K,1,VDD2 K,2,VSS K,3,VDD2 K,4,VSS K,5,DNU K,6,NB K,7,NB K,8,DNU K,9,VSS K,10,VDD2 K,11,VSS K,12,VDD2 L,1,NB L,2,NB L,3,NB L,4,NB L,5,NB L,6,NB L,7,NB L,8,NB L,9,NB L,10,NB L,11,NB L,12,NB M,1,NB M,2,NB M,3,NB M,4,NB M,5,NB M,6,NB M,7,NB M,8,NB M,9,NB M,10,NB M,11,NB M,12,NB N,1,VDD2 N,2,VSS N,3,VDD2 N,4,VSS N,5,DNU N,6,NB N,7,NB N,8,DNU N,9,VSS N,10,VDD2 N,11,VSS N,12,VDD2 P,1,VSS P,2,CA1_b P,3,VSS P,4,CKE_b P,5,NC P,6,NB P,7,NB P,8,CK_t_b P,9,CK_c_b P,10,VSS P,11,CA5_b P,12,VSS R,1,VDD2 R,2,CA0_b R,3,NC R,4,CS_b R,5,VDD2 R,6,NB R,7,NB R,8,VDD2 R,9,CA2_b R,10,CA3_b R,11,CA4_b R,12,VDD2 T,1,VSS T,2,ODT_CA_b T,3,VSS T,4,VDD1 T,5,VSS T,6,NB T,7,NB T,8,VSS T,9,VDD1 T,10,VSS T,11,RESET_n T,12,VSS U,1,VDD1 U,2,DQ3_b U,3,VDDQ U,4,DQ4_b U,5,VDD2 U,6,NB U,7,NB U,8,VDD2 U,9,DQ12_b U,10,VDDQ U,11,DQ11_b U,12,VDD1 V,1,VSS V,2,DQ2_b V,3,DQS0_c_b V,4,DQ5_b V,5,VSS V,6,NB V,7,NB V,8,VSS V,9,DQ13_b V,10,DQS1_c_b V,11,DQ10_b V,12,VSS W,1,VDDQ W,2,VSS W,3,DQS0_t_b W,4,VSS W,5,VDDQ W,6,NB W,7,NB W,8,VDDQ W,9,VSS W,10,DQS1_t_b W,11,VSS W,12,VDDQ Y,1,VSS Y,2,DQ1_b Y,3,DMI0_b Y,4,DQ6_b Y,5,VSS Y,6,NB Y,7,NB Y,8,VSS Y,9,DQ14_b Y,10,DMI1_b Y,11,DQ9_b Y,12,VSS AA,1,DNU AA,2,DQ0_b AA,3,VDDQ AA,4,DQ7_b AA,5,VDDQ AA,6,NB AA,7,NB AA,8,VDDQ AA,9,DQ15_b AA,10,VDDQ AA,11,DQ8_b AA,12,DNU AB,1,DNU AB,2,DNU AB,3,VSS AB,4,VDD2 AB,5,VSS AB,6,NB AB,7,NB AB,8,VSS AB,9,VDD2 AB,10,VSS AB,11,DNU AB,12,DNU
Note: ODT_CA_a and ODT_CA_b carry footnote “1)” in the datasheet indicating they are wired to Rank 0 ODT(CA) pads; other ranks’ ODT(CA) pads (if present) are disabled in the package.
Want me to attach this CSV to the project or proceed to place and wire this DRAM relative to the MPU for x32 routing?
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