Pin Function Grouping for nRF52840

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Created 5 tasks.
1/5 Read current part metadata, symbol pins, footprint/layout, BOM, assets, and existing docs

Read current part metadata, symbol pins, footprint/layout, BOM, assets, and existing docs

Find or verify the official nRF52840-QFAA-F-R datasheet URL and update part property if missing

Extract datasheet pin/package/key specifications

Cross-check symbol, footprint, pin descriptions, and properties against datasheet

Create a detailed audit project file and summarize mismatches

Accessed knowledge for the next task.
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adrian95

Looking at the datasheet of this component, can you group together pins by their functions? for example for Power, 3v3, gnd_1 gnd_2 etc
Also can you place them into their respective sections based on their functions
NOTE: If you group them, can you not add the same pin if you already added them in a group? You should know which pin function is common for its function

flux

I’ll update the nRF52840 symbol organization by assigning each pin to one functional section and one pin group only, using the datasheet pin functions as the source of truth. I’ll first inspect the current pins/properties, then apply grouped sections and verify there are no duplicate group assignments.

flux

Done — I grouped all 49 nRF52840-QFAA terminals into mutually exclusive functional sections and updated Section, Pin Group, Pin Type, and Pin Description properties. I also created the detailed reference file here: nRF52840-QFAA-F-R Pin Grouping.
No pin was assigned to more than one functional section; multifunction pins keep their alternate functions in the descriptions.
Run ERC/DRC
Review pin groups
Check decoupling
Clean descriptions
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Files

Pins

Symbol

Layout

3D View

nRF52840-QFAA-F-R Pin Grouping
Purpose: organize the 49 terminals of the nRF52840-QFAA QFN48 symbol into mutually exclusive functional sections. Each physical pin is assigned to exactly one Section and one Pin Group; multifunction capabilities are retained in the Pin Description rather than duplicating the pin in multiple groups.
Source basis: Nordic nRF52840 Product Specification pin naming/function conventions, the current part terminal list, and official Nordic documentation lookup. The uploaded PDF search did not expose the full QFN48 pin table as extractable text, so the symbol's pin-numbered terminal names were cross-checked against Nordic's known QFN48 naming conventions.
Functional sections used

Table

SectionIncluded pinsRationale
Power Supply1, 12, 17, 25, 32, 33, 34, 37, 45, 46, 47, 48, 49VDD, VSS/VSS_PA, exposed pad, DCC, and DEC regulator/decoupling pins.
Clock2, 3, 35, 36LF crystal pins XL1/XL2 and HF crystal pins XC1/XC2.
Analog4, 5, 39, 40, 41, 42, 43, 44GPIO pins with SAADC analog input functions AIN0-AIN7.
GPIO7, 8, 13, 14, 15, 18, 19, 20, 21, 22, 23, 38General digital GPIO without a higher-priority dedicated symbol group.
Debug6, 9, 10, 11, 24, 26, 27SWD and trace pins.
Reset16P0.18/nRESET, separated for visibility because reset is a board-level control signal.
Interface29, 30NFC antenna pins NFC1/NFC2.
Communication312.4 GHz RF antenna pin ANT.
MISC28No-connect pin.
Pin-by-pin assignments

Table

PinTerminalSectionPin GroupPin TypeDescription
1DEC1Power SupplyPowerPower Out1.1 V regulator supply decoupling; connect required capacitor per Nordic reference design.
2P0.00XL1ClockCrystalBi-DirectionalGPIO P0.00; 32.768 kHz low-frequency crystal input XL1.
3P0.01_XL2ClockCrystalBi-DirectionalGPIO P0.01; 32.768 kHz low-frequency crystal output XL2.
4P0.04_AIN2AnalogADCBi-DirectionalGPIO P0.04; SAADC analog input AIN2.
5P0.05AIN3AnalogADCBi-DirectionalGPIO P0.05; SAADC analog input AIN3.
6P0.07TRACECLKDebugDebugBi-DirectionalGPIO P0.07; trace buffer clock output TRACECLK.
7P0.08GPIOPABi-DirectionalGeneral purpose I/O P0.08.
8P1.08GPIOPBBi-DirectionalGeneral purpose I/O P1.08.
9P1.09TRACEDATA3DebugDebugBi-DirectionalGPIO P1.09; trace buffer data output TRACEDATA[3].
10P0.11TRACEDATA2DebugDebugBi-DirectionalGPIO P0.11; trace buffer data output TRACEDATA[2].
11P0.12TRACEDATA1DebugDebugBi-DirectionalGPIO P0.12; trace buffer data output TRACEDATA[1].
12VDD_1Power SupplyVDDPower InMain VDD power supply input.
13P0.13GPIOPABi-DirectionalGeneral purpose I/O P0.13.
14P0.14GPIOPABi-DirectionalGeneral purpose I/O P0.14.
15P0.17GPIOPABi-DirectionalGeneral purpose I/O P0.17.
16P0.18NRESETResetReset / GPIOBi-DirectionalGPIO P0.18; configurable system reset nRESET.
17VDD_2Power SupplyVDDPower InMain VDD power supply input.
18P0.19GPIOPABi-DirectionalGeneral purpose I/O P0.19.
19P0.20GPIOPABi-DirectionalGeneral purpose I/O P0.20.
20P0.21GPIOPABi-DirectionalGeneral purpose I/O P0.21.
21P0.22GPIOPABi-DirectionalGeneral purpose I/O P0.22.
22P0.23GPIOPABi-DirectionalGeneral purpose I/O P0.23.
23P0.24GPIOPABi-DirectionalGeneral purpose I/O P0.24.
24P1.00TRACEDATA0DebugDebugBi-DirectionalGPIO P1.00; trace buffer data output TRACEDATA[0], also used for SWO.
25VDD_3Power SupplyVDDPower InMain VDD power supply input.
26SWDIODebugSWDBi-DirectionalSerial wire debug data for programming and debug.
27SWDCLKDebugSWDInputSerial wire debug clock input for programming and debug.
28NCMISCNo connectNot ConnectedNo internal connection; leave unconnected.
29P0.09NFC1InterfaceNFC antenna / GPIOBi-DirectionalGPIO P0.09; NFC antenna connection NFC1.
30P0.10NFC2InterfaceNFC antenna / GPIOBi-DirectionalGPIO P0.10; NFC antenna connection NFC2.
31ANTCommunication2.4 GHz RFPassiveSingle-ended 2.4 GHz radio antenna connection; follow Nordic RF reference layout.
32VSS_PAPower SupplyVSSGroundGround for radio power amplifier supply.
33DEC6Power SupplyPowerPower Out1.3 V radio regulator supply decoupling; decouple per Nordic reference circuit.
34DEC3Power SupplyPowerPower OutInternal supply decoupling pin; connect capacitor per Nordic reference circuit.
35XC1ClockCrystalInput32 MHz high-frequency crystal connection XC1.
36XC2ClockCrystalOutput32 MHz high-frequency crystal connection XC2.
37VDD_4Power SupplyVDDPower InMain VDD power supply input.
38P1.15GPIOPBBi-DirectionalGeneral purpose I/O P1.15.
39P0.03AIN1AnalogADCBi-DirectionalGPIO P0.03; SAADC analog input AIN1.
40P0.02AIN0AnalogADCBi-DirectionalGPIO P0.02; SAADC analog input AIN0.
41P0.28AIN4AnalogADCBi-DirectionalGPIO P0.28; SAADC analog input AIN4.
42P0.29AIN5AnalogADCBi-DirectionalGPIO P0.29; SAADC analog input AIN5.
43P0.30AIN6AnalogADCBi-DirectionalGPIO P0.30; SAADC analog input AIN6.
44P0.31AIN7AnalogADCBi-DirectionalGPIO P0.31; SAADC analog input AIN7.
45VSS_1Power SupplyVSSGroundGround VSS.
46DEC4Power SupplyPowerPower Out1.3 V regulator supply decoupling; connect/decouple with DEC6 per Nordic guidance.
47DCCPower SupplyPowerPower OutDC/DC converter output node; connect external inductor/capacitors per Nordic reference circuit.
48VDD_5Power SupplyVDDPower InMain VDD power supply input.
49VSS_2Power SupplyVSSGroundExposed die pad VSS; connect to ground for operation, thermal, and RF performance.
Verification
  • All 49 physical pins are represented.
  • Each pin has exactly one Section value.
  • Each pin has exactly one Pin Group value.
  • No pin was duplicated across functional groups.
  • Pin descriptions preserve important alternate functions for GPIO/analog, GPIO/clock, GPIO/NFC, GPIO/reset, and GPIO/trace pins.

  • Functional sections used

  • Pin-by-pin assignments

  • Verification