I reviewed the part metadata, current part project, and the official datasheet workflow. For part-project verification, the key checks are: confirm an existing Datasheet URL, use the datasheet as the source of truth for package/pin metadata, and compare every terminal and footprint pad against the datasheet pin list .
What I foundPart metadata
The project already has a Datasheet URL set, so I did not need to search the web or update that property. The existing project properties show:
MPN: MP2731GQC-0000-Z
Manufacturer: Monolithic Power Systems (MPS)
Package: QFN
Designator Prefix: IC
From the official datasheet, the device is:
MP2731GQC-0000-Z
Monolithic Power Systems, Inc.
QFN-26 (3.5 mm x 3.5 mm) / mechanical package name 26L FCQFN (3.5 x 3.5 mm)
26 pins
Description: 4.5 A, I2C-controlled switch-mode battery charger with NVDC power path and USB OTG
Key specs from the datasheet
Input operating range: 3.7 V to 16 V
Sustainable voltage: 22 V
Charge current: up to 4.5 A
Switching frequency: 1.35 MHz
OTG output: 4.8 V to 5.5 V
OTG current: up to 3.0 A
Junction temperature: -40°C to +125°C
Package: QFN-26, 3.5 mm x 3.5 mm
Cross-check summaryGood matches
The overall identity looks correct:
MPN matches the datasheet.
Manufacturer matches the datasheet.
The project is clearly intended to represent the MP2731 charger PMIC.
There are major symbol/footprint consistency problems relative to the datasheet:
1. Pin count mismatch
Datasheet: 26 pins
Current schematic symbol: 30 terminal components
Current footprint: 30 pads visible in the layout data
This is the biggest issue. The part project should match the datasheet pin count exactly, including any exposed pad only if the datasheet explicitly lists it as a pin . The extracted datasheet content did not identify an exposed pad pin for this package, so the current 30-pin symbol/30-pad footprint appears incorrect.
2. Extra pins that should not exist
The datasheet pin table ends at pin 26 , but the current symbol includes:
These are not present in the extracted datasheet pin list and should be flagged as likely erroneous.
3. Missing / misassigned repeated pins
The datasheet lists repeated functions at these exact pin numbers:
DP on pins 1 and 26
PGND on pins 5, 6, 7
VREF on pins 13, 14
SCL on pins 19, 20
In the current project:
Pin 14 is PGND_4, but the datasheet says pin 14 should be a second VREF.
Pins 28 and 29 are extra PGND entries not supported by the datasheet.
Pin 30 is an extra SCL entry not supported by the datasheet.
The symbol uses split naming such as DP_1, DP_2, SCL_1, SCL_2, which is acceptable stylistically, but the pin numbers must still match the datasheet exactly.
4. Pin descriptions are effectively missing
The current terminals have Pin Number and Pin Type, but I did not see meaningful Pin Description properties populated on the symbol terminals. The verification workflow expects short pin descriptions to be set from the datasheet for IC-style parts . So this is an incompleteness issue, even where pin names are otherwise correct.
5. Pin types are all Unspecified
Every terminal I inspected had Pin Type: Unspecified, including STAT, BST, IN, SYS, and others. For a part project, pin types should be assigned from the datasheet mapping rules, such as:
IN -> Power In
PGND, AGND -> Ground
STAT, INT -> Output
CE, OTG, DISC, ILIM, NTC -> Input
SDA -> Bi-Directional
SCL -> Input
SYS, possibly VREF depending on intended modeling -> likely Power Out / Output context-dependent
Using exact datasheet-derived pin typing is recommended for ERC quality .
Footprint assessment
The layout contains one footprint with 30 pads, mirroring the 30 terminals in the symbol. Since the official package is QFN-26 / 26L FCQFN, this strongly suggests the footprint is also mismatched to the datasheet package definition. In other words:
Symbol pin count is wrong
Footprint pad count is wrong
Symbol and footprint are internally consistent with each other, but both are inconsistent with the official datasheet
Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power