Part Information Review and Datasheet Update
1:57
Thought for 2 sec
1/3 Read current symbol section/group/order properties for all terminals
Thought for 6 sec
Read schematic.
Read "Pin Description table pins 1 through 30 MAX77960B MAX77961B functional descriptions" in MAX77960B-MAX77961B.pdf.
Read "Typical Application Circuit MAX77960B MAX77961B pin groups CHGIN SYS BATT I2C configuration status" in MAX77960B-MAX77961B.pdf.
Read MAX77960B-MAX77961B.pdf.
Read MAX77960B-MAX77961B.pdf.
Thought for 1 sec
2/3 Compare grouping against datasheet functional pin groups
Thought for 21 sec
Thought for 3 sec
3/3 tasks completed.
Thought for a moment
STBY should not be in Status/Interrupt, DISQBAT should be Hardware Control, AVL/PVL should be Bias Supplies, CSINP/CSINN should be CHGIN/Input Current Sense, and BST/LX pins should be Switching Power Stage rather than generic Power Input.0:10
Thought for 6 sec
Thought for a moment
1:21
Thought for 5 sec
1/2 Update Section and Pin Group properties for all 30 terminals
Read 1 knowledge entry.
Thought for 15 sec
Thought for 4 sec
2/2 Verify the updated symbol section/group organization
Thought for 1 sec
Read schematic.
Thought for 2 sec
Completed 2 design checks.
Thought for 2 sec
2/2 tasks completed.
Thought for a moment
CHGIN / Input Current Sense, Switching Power Stage, System / Battery Power Path, Hardware Control, Charger Programming, Bias Supplies, I2C Communication, Status / Interrupt Outputs, Thermal / Battery Monitor, and Ground. Verified afterward, and the relevant terminal review checks returned no issues.Table
| Pin | Datasheet name | Datasheet function summary | Project symbol terminal present | Project pin type |
|---|---|---|---|---|
| 1 | BST1 | High-side input MOSFET driver supply; bypass to LX1 with 0.22 uF | Yes | Input |
| 2 | CHGIN | Buck-boost charger input; reverse-mode buck output; bypass to PGND | Yes | Input |
| 3 | LX1 | Inductor connection one | Yes | Unspecified |
| 4 | PGND | Power ground for buck-boost low-side MOSFETs | Yes | Power In |
| 5 | LX2 | Inductor connection two | Yes | Unspecified |
| 6 | SYS | System supply output; bypass to PGND | Yes | Power In |
| 7 | OTGEN | Active-high OTG enable input | Yes | Input |
| 8 | DISQBAT | Active-high QBAT disconnect / charge-disable input | Yes | Input |
| 9 | BST2 | High-side output MOSFET driver supply; bypass to LX2 with 0.22 uF | Yes | Power In |
| 10 | BATSN | Battery differential sense negative input | Yes | Input |
| 11 | BATSP | Battery differential sense positive input | Yes | Input |
| 12 | BATT | Battery power connection; bypass to PGND; all BATT pins together externally | Yes | Power In |
| 13 | THM | Thermistor input | Yes | Input |
| 14 | SCL | I2C clock input | Yes | Input |
| 15 | SDA | I2C data; open-drain output | Yes | Output |
| 16 | STAT | Charger status; active-low open-drain output; 10 kOhm pullup | Yes | Output |
| 17 | INOKB | Input/OTG power-OK; active-low open-drain output | Yes | Output |
| 18 | INTB | Active-low open-drain interrupt output | Yes | Output |
| 19 | SYSA | SYS voltage sensing input for SYS UVLO/OVLO | Yes | Input |
| 20 | GND | Analog ground | Yes | Power Out |
| 21 | INLIM | Input current limit programming input | Yes | Input |
| 22 | CNFG | Device configuration input; programs switching frequency and cell count | Yes | Input |
| 23 | ISET | Fast-charge current programming input | Yes | Input |
| 24 | VSET | Charge termination voltage programming input | Yes | Input |
| 25 | ITO | Top-off current programming input | Yes | Input |
| 26 | AVL | Analog voltage supply for low-noise circuits; bypass to GND and connect to PVL through 4.7 ohm | Yes | Power In |
| 27 | PVL | Internal bias regulator high-current output bypass; not recommended for external loads except pullups | Yes | Output |
| 28 | STBY | Active-high standby input | Yes | Input |
| 29 | CSINP | Input current-sense positive input | Yes | Input |
| 30 | CSINN | Input current-sense negative input | Yes | Input |
Pin Description properties were present. The datasheet descriptions above should be copied into the terminals if this part is intended for library-quality reuse.Power In, but the datasheet describes it as System Supply Output.Power Out; ground pins are normally ground/passive/power reference rather than output.Power In; should be ground/power ground.Output, while I2C SDA is bidirectional/open-drain in practical use; the datasheet text says open-drain output.Unspecified; they should be switch/inductor connection pins, typically passive/power-switching nodes.Input, but it is a driver supply bootstrap pin.Table
| Current section | Pins assigned |
|---|---|
| Power Input | BST1, CHGIN, LX1, LX2, BST2 |
| System Power | SYS, DISQBAT, SYSA |
| Battery / Charging | BATSN, BATSP, BATT, CSINP, CSINN |
| Thermal / Monitoring | THM |
| I2C Communication | SCL, SDA |
| Status / Interrupt | STAT, INOKB, INTB, STBY |
| Control / Configuration | OTGEN, INLIM, CNFG, ISET, VSET, ITO, AVL, PVL |
| Ground | PGND, GND |
STBY is currently in Status / Interrupt, but the datasheet defines it as an active-high control input. It belongs with hardware control pins, not status outputs.DISQBAT is currently in System Power, but the datasheet defines it as an active-high control input for the BATT-to-SYS QBAT FET / charging disable behavior. It is better grouped with hardware control pins.OTGEN is currently in Control / Configuration; that is acceptable, but it is specifically a hardware mode-control input and should be near DISQBAT and STBY.AVL and PVL are currently in Control / Configuration, but the datasheet defines them as internal analog/bias supply bypass pins. They should be in a bias/internal supply section rather than grouped with resistor-programming pins.CSINP and CSINN are currently in Battery / Charging, but the datasheet defines them as input current-sense pins associated with CHGIN/input current monitoring. They would be clearer in an input current-sense / CHGIN input section.BST1, BST2, LX1, and LX2 are currently in Power Input. These are switching power-stage pins and bootstrap driver supplies, not simple input power pins. A dedicated switching power-stage section would be clearer.Table
| Recommended section | Pins |
|---|---|
| CHGIN / Input Current Sense | CHGIN, CSINP, CSINN |
| Switching Power Stage | BST1, LX1, BST2, LX2 |
| System / Battery Power Path | SYS, SYSA, BATT, BATSP, BATSN |
| Hardware Control | OTGEN, DISQBAT, STBY |
| Charger Programming | INLIM, CNFG, ISET, VSET, ITO |
| Bias Supplies | AVL, PVL |
| I2C Communication | SCL, SDA |
| Status / Interrupt Outputs | STAT, INOKB, INTB |
| Thermal / Battery Monitor | THM |
| Ground | PGND, GND |
STBY out of status, moving DISQBAT into hardware control, separating AVL/PVL as bias supplies, and separating CSINP/CSINN as CHGIN input current-sense pins.Welcome 👋
Flux accelerates your PCB design with AI.
Create your account to start using this component and bring your ideas to life.