Part Audit and Datasheet Review


Completed the audit and set the official Analog Devices datasheet URL: https://www.analog.com/media/en/technical-documentation/data-sheets/ltm4712.pdf
Summary:
  • Symbol: 144 terminals match the datasheet 144-ball assignment.
  • Footprint: 144 pads match the CSP_BGA ball count.
  • Key flags: project name uses LTM4712IY-PBF while the official order code is LTM4712IY#PBF; pin descriptions are mostly missing; several pin types should be refined, especially INTVCC, VOUT, and SW1/SW2.
  • Footprint pitch/pad/body dimensions should be spot-checked against the datasheet mechanical drawing before release.
I saved the detailed report here: Part Audit: LTM4712IY#PBF
Fix the MPN formatting and missing pin descriptions from the datasheet. Also please convert the symbol to parametric style, and place each pin into the correct section based on the datasheet. also add pin group and pin orientation for all the pins.
I’ll update the official MPN formatting, add datasheet-derived pin descriptions, and restructure the symbol metadata into parametric sections/groups with orientations and ordering.
The official MPN/project name and all unique signal/power-control pins are updated. I’m applying the repeated power/ground ball metadata next, which is the bulk of the 144-ball symbol.
Done.
  • Renamed the project to the official MPN format: LTM4712IY#PBF.
  • Converted the symbol terminals to Parametric style.
  • Added datasheet-derived Pin Description, Section, Pin Group, Pin Orientation, and Terminal Order metadata across the 144-ball symbol.
  • Refined key pin types, including INTVCC as power output, VOUT as power output, and SW1/SW2 as passive switch/test nodes.
  • Verified representative signal, power, switch, SGND, and GND pins; no missing parametric metadata was surfaced by the project index or review checks.
Run ERC check
Find missing metadata
Verify pin sections
Export pin report

Name
Pin #
Type
Part Type
Pin Description
Pin Group
Pin Orientation
Section
GND
A1
Power Out
Terminal
Power ground
Ground
Bottom
Ground
GND
A2
Power Out
Terminal
Power ground
Ground
Bottom
Ground
ISN
A3
Input
Terminal
Average current sense negative
Current Sense
Left
Analog
ISP
A4
Input
Terminal
Average current sense positive
Current Sense
Left
Analog
IMON
A5
Output
Terminal
Current monitor output
Current Sense
Right
Analog
CLKOUT
A6
Output
Terminal
Synchronization clock output
Synchronization
Right
Clock
FREQ
A7
Input
Terminal
Switching frequency set
Frequency Control
Left
Clock
PGOOD
A8
Output
Terminal
Open-drain power good output
Status
Right
Control
PHMODE
A9
Input
Terminal
Clock phase mode select
Mode Control
Left
Control
MODE
A10
Input
Terminal
FCM pulse-skipping select
Mode Control
Left
Control
SS
A11
Input
Terminal
Soft-start capacitor input
Soft Start
Left
Control
GND
A12
Power Out
Terminal
Power ground
Ground
Bottom
Ground
GND
B1
Power Out
Terminal
Power ground
Ground
Bottom
Ground
GND
B2
Power Out
Terminal
Power ground
Ground
Bottom
Ground
INTVCC
B3
Power Out
Terminal
Internal 5V regulator output
Bias Supply
Top
Power
EXTVCC
B4
Power In
Terminal
External LDO supply input
Bias Supply
Top
Power
ISET
B5
Input
Terminal
Average current limit set
Current Limit
Left
Analog
SYNC
B6
Input
Terminal
External synchronization input
Synchronization
Left
Clock
SGND
B7
Power Out
Terminal
Signal ground
Ground
Bottom
Ground
RUN
B8
Input
Terminal
Enable control input
Enable
Left
Control
FB
B9
Input
Terminal
Error amplifier feedback input
Feedback
Left
Analog
COMPa
B10
Passive
Terminal
Compensation amplifier node
Compensation
Left
Analog
COMPb
B11
Passive
Terminal
Internal compensation node
Compensation
Left
Analog

LTM4712IY#PBF