Pin Function Grouping for Component

flux

Done. I generalized the functional groups across all 81 pins and added Section to every pin with the same value as its Pin Group.
Open items:
  • Some generalized labels like Ethernet and Status/Debug are accepted but not in Flux’s suggested autocomplete list.
Suggested next steps:
  1. Review the symbol sections visually.
  2. If desired, I can further reduce groups to only Flux-suggested values like Power, Ground, Control, Interface, Analog, Debug, and Clock.
adrian95

adrian95

Use only Flux-suggested values for Pin Group and Section across all pins.

flux

I’ll normalize the remaining custom group labels to Flux-suggested values only, then verify every pin’s Pin Group and Section uses allowed values.

flux

Done. I normalized all pins to Flux-suggested Pin Group and Section values only, keeping each pin’s Section equal to its Pin Group.
Open items:
  • None.
Suggested next steps:
  1. Review the symbol layout by section.
  2. Run a final part QA check before publishing.
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LAN9254-I/JRX Part Review
Source
Key Part Information
  • MPN: LAN9254-I/JRX
  • Manufacturer: Microchip Technology
  • Device: EtherCAT SubDevice/slave controller with integrated dual 10/100 Ethernet PHYs.
  • Package/order code: JRX = 80-pin TQFP-EP.
  • Exposed pad: VSS bottom pad, connect to ground with via field.
  • Pad count in Flux project: 81 = 80 perimeter pins + exposed pad.
  • Operating temperature for -I: -40°C to +85°C.
  • Supply operating ranges from datasheet:
    • VDD12TX1, VDD12TX2, OSCVDD12, VDDCR: 1.14 V to 1.26 V
    • VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33: 3.0 V to 3.6 V
    • VDDIO: 1.62 V to 3.6 V
Functional Pin Grouping Applied
Each physical pin is assigned to exactly one primary functional group. Multifunction pins were grouped by their most common/primary interface role from the datasheet rather than duplicated across every alternate function.
Clock/Oscillator
  • 1 OSCI
  • 2 OSCO
  • 8 CLK_25/CLK_25_EN/XTAL_MODE
Ground
  • 4 OSCVSS
  • EPAD VSS
Power - 1.2V Core/Oscillator
  • 3 OSCVDD12
  • 6 VDDCR
  • 31 VDDCR
  • 51 VDDCR
Power - I/O Supply
  • 16 VDDIO
  • 27 VDDIO
  • 39 VDDIO
  • 50 VDDIO
  • 60 VDDIO
Power - 3.3V Analog
  • 5 VDD33
  • 74 VDD33BIAS
Power - 3.3V Ethernet PHY
  • 67 VDD33TXRX1
  • 80 VDD33TXRX2
Power - 1.2V Ethernet PHY
  • 72 VDD12TX1
  • 75 VDD12TX2
Configuration/Straps
  • 7 REG_EN
Reset/Test
  • 11 RST#
  • 54 TESTMODE
LED/Status/JTAG/Straps
  • 9 ERRLED/PME/100FD_B/LEDPOL4
  • 58 RUNLED/STATE_RUNLED/E2PSIZE/EE_EMUL0/LEDPOL3
  • 59 LINKACTLED1/TDI/CHIP_MODE1/LEDPOL1
  • 61 LINKACTLED0/TDO/CHIP_MODE0/100FD_A/LEDPOL0
EEPROM/JTAG
  • 55 EESDA/TMS/EE_EMUL1
  • 56 EESCL/TCK/EE_EMUL2
Control/Interrupt/Sync
  • 10 WAIT_ACK/PME/LATCH0/EE_EMUL_SPI3
  • 22 SYNC1/LATCH1/PME
  • 43 SYNC0/LATCH0/PME
  • 57 IRQ/LATCH1
  • 65 DIGIO30/LATCH0
  • 66 DIGIO31/LATCH1
Control Bus/GPIO
  • 35 CS/DIGIO13/GPI13/GPO13/MII_RXD1
  • 37 WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2
  • 38 RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3
Address/Digital I/O
  • 12 A5/DIGIO16
  • 13 A6/DIGIO17
  • 17 A7/DIGIO18
  • 18 A8/DIGIO19
  • 23 A9/DIGIO20
  • 24 A10/DIGIO21
  • 25 A11/DIGIO22
  • 32 A1/ALELO/OE_EXT/MII_CLK25/EE_EMUL_SPI2
  • 33 A3/BE0/DIGIO11/GPI11/GPO11/MII_RXDV
  • 34 A4/BE1/DIGIO12/GPI12/GPO12/MII_RXD0
  • 36 A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/EE_EMUL_ALELO_POL/MII_LINKPOL/LEDPOL2
  • 40 A12/DIGIO23
  • 42 A13/DIGIO24
  • 44 A14/DIGIO25
  • 45 A15/DIGIO26
  • 46 END_SEL/DIGIO27
  • 47 BE0/DIGIO28
  • 64 BE1/DIGIO29
Data/SPI/MII/GPIO
  • 14 D2/AD2/SOF/SIO2/EE_EMUL_SPI0
  • 15 D1/AD1/EOF/SO/SIO1
  • 19 D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1
  • 20 D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0
  • 21 D0/AD0/WD_STATE/SI/SIO0
  • 26 D9/AD9/LATCH_IN/SCK
  • 28 D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1/100FD_B
  • 29 D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0/100FD_A
  • 30 D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN
  • 41 A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER
  • 48 D3/AD3/WD_TRIG/SIO3/EE_EMUL_SPI1
  • 49 D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK
  • 52 D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC
  • 53 D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO
  • 62 D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK
  • 63 D5/AD5/OUTVALID/SCS#
Ethernet Port A
  • 68 TXNA
  • 69 TXPA
  • 70 RXNA
  • 71 RXPA
Analog Bias
  • 73 RBIAS
Ethernet Port B
  • 76 RXPB
  • 77 RXNB
  • 78 TXPB
  • 79 TXNB
Symbol / Footprint Cross-Check
  • Symbol exposes 81 terminals matching the package: pins 1-80 plus EPAD/VSS.
  • Footprint contains 81 pads matching 80-TQFP-EP plus exposed pad.
  • Footprint text indicates TQFP-EP80_JRX_MCH, body approximately 12 mm x 12 mm, 0.5 mm pitch, consistent with JRX package.
  • Exposed pad exists as VSS and is described as ground with via field requirement.
Mismatches / Issues Flagged
  • No pin-number mismatches were found in the Flux symbol versus the datasheet pin assignment table for pins 1-80 plus exposed pad.
  • The OCR extraction of the datasheet table showed TXNB as pin 78 in one snippet, but the package pinout and project symbol correctly use TXPB = 78 and TXNB = 79.
  • Many pins initially had Pin Type: Unspecified; this was updated with more appropriate pin types and descriptions.
  • The official Microchip PDF URL should be preferred for traceability even though the project also has an uploaded datasheet asset URL.

  • Source

  • Key Part Information

  • Functional Pin Grouping Applied

  • Clock/Oscillator

  • Ground

  • Power - 1.2V Core/Oscillator

  • Power - I/O Supply

  • Power - 3.3V Analog

  • Power - 3.3V Ethernet PHY

  • Power - 1.2V Ethernet PHY

  • Configuration/Straps

  • Reset/Test

  • LED/Status/JTAG/Straps

  • EEPROM/JTAG

  • Control/Interrupt/Sync

  • Control Bus/GPIO

  • Address/Digital I/O

  • Data/SPI/MII/GPIO

  • Ethernet Port A

  • Analog Bias

  • Ethernet Port B

  • Symbol / Footprint Cross-Check

  • Mismatches / Issues Flagged