Updated all 28 terminals with datasheet-derived Pin Type and short Pin Description values, and normalized ENV_SCL_, SA0/H_MOSI_, and H_SDA/H_MISO/TX_ by removing trailing underscores.
Open items:
Part review checks were queried after the update, but no component review check entries were returned for this part project.
I verified directly in the schematic that the updated pin metadata and normalized names are present.
Suggested next steps:
If you want, I can also update the earlier bno085-part-review document with the completed fixes.
Run a visual footprint/land-pattern check against the datasheet package drawing.
UART-SHTP: 3 Mbit/s, 8 data bits, 1 stop bit, no parity
CAP pin: external 100 nF to GND
32 kHz clock option: external 32.768 kHz clock/crystal on XIN32/XOUT32; CEVA recommends 50 ppm tolerance and 12.5 pF load crystal
Typical BNO085 6/9-axis sensor fusion at 100 Hz: VDDIO 3.50 mA, VDD 7.50 mA, total 35.25 mW
Datasheet pin table cross-check
Table
Pin
Datasheet name / function
Project terminal
Result
1
RESV_NC, no connect
RESV_NC_1
Match
2
GND
GND_1
Match
3
VDD
VDD
Match
4
BOOTN
BOOTN
Match
5
PS1
PS1
Match
6
PS0/WAKE
PS0/WAKE
Match
7
RESV_NC, no connect
RESV_NC_2
Match
8
RESV_NC, no connect
RESV_NC_3
Match
9
CAP, 100 nF to GND
CAP
Match
10
CLKSEL0
CLKSEL0
Match
11
NRST
NRST
Match
12
RESV_NC, no connect
RESV_NC_4
Match
13
RESV_NC, no connect
RESV_NC_5
Match
14
H_INTN
H_INTN
Match
15
ENV_SCL
ENV_SCL_
Minor naming mismatch: trailing underscore
16
ENV_SDA
ENV_SDA
Match
17
SA0/H_MOSI
SA0/H_MOSI_
Minor naming mismatch: trailing underscore
18
H_CSN
H_CSN
Match
19
H_SCL/SCK/RX
H_SCL/SCK/RX
Match
20
H_SDA/H_MISO/TX
H_SDA/H_MISO/TX_
Minor naming mismatch: trailing underscore
21
RESV_NC, no connect
RESV_NC_6
Match
22
RESV_NC, no connect
RESV_NC_7
Match
23
RESV_NC, no connect
RESV_NC_8
Match
24
RESV_NC, no connect
RESV_NC_9
Match
25
GND
GND_2
Match
26
XOUT32/CLKSEL1
XOUT32/CLKSEL1
Match
27
XIN32
XIN32
Match
28
VDDIO
VDDIO
Match
Symbol and pin-description findings
Pin count is correct at 28 terminals.
Pin numbering aligns with the datasheet for all 28 pins.
Terminal names mostly match the datasheet.
Minor naming mismatches: ENV_SCL_, SA0/H_MOSI_, and H_SDA/H_MISO/TX_ include a trailing underscore not present in the datasheet names. This may be intentional Flux naming to avoid syntax/special-character conflicts, but it is not exact datasheet text.
All terminal Pin Type properties are currently Unspecified. The datasheet provides electrical direction/type information, so pin types could be improved:
Pin descriptions are not populated as explicit Pin Description properties on the terminals; adding them would make the part easier to audit and use.
Footprint findings
Layout has 28 pad nodes, matching the 28-pin LGA package.
The footprint is named as the default footprint for the published part and includes fab/silk/text shapes.
The current layout inspection did not expose pad geometry, pitch, or body dimensions, so I could verify pad count but not fully validate the land pattern dimensions against the datasheet package drawing.
Mismatches / open issues
Pin Type properties are all Unspecified — should be updated to match datasheet direction/type.
Pin Description properties are absent — recommended to add datasheet-based descriptions for each terminal.
Minor terminal-name differences — trailing underscores on pins 15, 17, and 20.
Footprint geometry not fully verifiable from available layout output — pad count matches; mechanical dimensions/land pattern should be checked visually or with a footprint geometry export if available.
Recommendation
The part is broadly correct for MPN, manufacturer, datasheet URL, 28-pin LGA pin count, and pin-number mapping. The next quality step is to enrich the terminal metadata with datasheet-based Pin Type, Pin Description, and possibly normalized pin names if Flux allows those names without syntax issues.