Part Review and Datasheet Verification

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adrian95

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

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I’ll inspect the existing part metadata, find or verify the official datasheet, update the Datasheet property if needed, then compare the symbol/footprint/pins against the datasheet and record the detailed findings in a project file.

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Reviewed the ADN4624BCPZ part against the official Analog Devices datasheet. The datasheet was already accessible in-project, so no Datasheet URL update was needed; the official URL is https://www.analog.com/media/en/technical-documentation/data-sheets/adn4622-4624.pdf.
Result: no blocking symbol pinout mismatch found for pins 1–32. Main flags are documentation/semantics: the 34 project pads appear to represent 32 leads plus split exposed pads for GND1/GND2, EPAD naming could be clearer, and GND pins are typed as Power Out rather than a ground/passive style.
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ADN4624BCPZ Part Review
Date: 2026-06-09
Sources
Available Part Information Reviewed
  • Project/part name: ADN4624BCPZ
  • Manufacturer part number: ADN4624BCPZ
  • Manufacturer: Analog Devices
  • Description: 5.7 kV RMS / 1.5 kV RMS, quad-channel LVDS 2.5 Gbps isolator, 0 reverse channels
  • Package: 32-lead LFCSP, 6 mm x 6 mm body, 0.75 mm package height
  • Package option: CP-32-32
  • Ordering guide entry: ADN4624BCPZ, tray quantity 490, RoHS-compliant Z suffix
  • Project pad count: 34 pads
  • Datasheet package pins: 32 leads plus exposed pad; the project appears to model the exposed pad as two separate ground pads/terminals, giving 34 total pads.
Key Datasheet Specs

Table

SpecDatasheet value
FunctionQuad-channel signal-isolated LVDS buffer/isolator
Max data rate2.5 Gbps per channel
Total bandwidth10 Gbps across four channels
Typical propagation delay2.15 ns
Max propagation delay2.8 ns
Typical random jitter0.82 ps rms
Typical total jitter40 ps p-p at BER 1e-12
LVDS complianceTIA/EIA-644-A signal levels
Supply voltage, recommendedVDD1/VDD2 = 1.7 V to 1.9 V; nominal 1.8 V
Supply current side 1140 mA typ, 175 mA max at f = 1.25 GHz
Supply current side 2115 mA typ, 140 mA max at f = 1.25 GHz, RL = 100 ohm
Operating temperature-40 C to +125 C
LFCSP isolation rating1.5 kV rms, 1 minute
LFCSP creepage/clearance/PCB clearance1.27 mm min
CMTI100 kV/us typical
Decoupling requirementBoth VDD1 pins and both VDD2 pins externally connected and bypassed to respective GND with 0.1 uF capacitors
Pin Cross-Check
The schematic symbol uses one terminal per pin/pad. The pin numbers and names match the datasheet LFCSP pin table for pins 1 through 32:

Table

Pin(s)Datasheet mnemonicProject symbolResult
1DIN1+DIN1+Match
2DIN1-DIN1-Match
3DIN2+DIN2+Match
4DIN2-DIN2-Match
5, 6, 21, 22, 27, 32NICNICMatch
7DIN3+DIN3+Match
8DIN3-DIN3-Match
9DIN4+DIN4+Match
10DIN4-DIN4-Match
11REFRESH1 active-low*REFRESH1Functionally match; active-low indicated by leading asterisk
12, 31GND1GND1Match
13, 30VDD1VDD1Match
14, 29VDD2VDD2Match
15, 28GND2GND2Match
16REFRESH2 active-low*REFRESH2Functionally match; active-low indicated by leading asterisk
17DOUT4-DOUT4-Match
18DOUT4+DOUT4+Match
19DOUT3-DOUT3-Match
20DOUT3+DOUT3+Match
23DOUT2-DOUT2-Match
24DOUT2+DOUT2+Match
25DOUT1-DOUT1-Match
26DOUT1+DOUT1+Match
EPADExposed pad, connect side 1 EPAD to GND1 and side 2 EPAD to GND2Project has extra GND1 pin 33 and GND2 pin 34Likely acceptable split-EPAD representation; consider renaming to EPAD_GND1 and EPAD_GND2 for clarity if supported
Symbol Pin-Type Cross-Check
  • DINx pins are marked Input: correct.
  • DOUTx pins are marked Output: correct.
  • REFRESHx pins are marked Input: correct.
  • NIC pins are marked Not Connected: correct.
  • VDDx pins are marked Power In: correct.
  • GNDx pins are marked Power Out in the project: acceptable for many schematic libraries as power net providers, but electrically they are ground reference pins. If strict ERC semantics are desired, Ground/Power Passive may be clearer.
Footprint Cross-Check
  • The footprint outline visible in layout is approximately 6.096 mm square around the package body, consistent with the 6 mm x 6 mm LFCSP body nominal and common courtyard/silk expansion.
  • Peripheral pads appear arranged on all four sides with 0.5 mm pitch, consistent with a 32-lead 6 mm x 6 mm LFCSP style package.
  • Project pad count is 34, while datasheet lead count is 32 plus exposed pad. This is not necessarily wrong because the ADN4624 LFCSP exposed pad is isolation-aware and must connect side 1 EPAD to GND1 and side 2 EPAD to GND2. The project likely models this as two exposed-pad copper areas, giving 32 leads + 2 EPAD regions.
  • I could verify pad labels and visible geometry, but the available layout readout did not expose full numeric pad dimensions for each pad. For final library signoff, compare pad widths/lengths and EPAD split geometry against the Analog Devices CP-32-32 land pattern/outline drawing.
Mismatches / Flags
  1. No functional pin-name mismatch found for pins 1-32.
  2. Pad count explanation needed: project has 34 pads vs datasheet 32 leads + EPAD. This appears intentional if pads 33 and 34 are the two exposed-pad regions tied to GND1 and GND2. Flag as acceptable but document explicitly.
  3. EPAD naming clarity: extra pads are named GND1/GND2 rather than EPAD_GND1/EPAD_GND2. This is electrically reasonable but less explicit.
  4. Pin 16 datasheet wording: the retrieved datasheet text says REFRESH2 is an “Active Low Enable for Side 1 Refresh Function,” but context and grounding instruction reference GND2/VDD2; this appears to be a datasheet text typo or OCR wording issue. The project symbol name *REFRESH2 is correct.
  5. GND pin type: Ground terminals are marked Power Out. Not a package mismatch, but Power Passive/Ground would be semantically cleaner if the platform supports it.
  6. Decoupling note: symbol/package correctly exposes both VDD1 pins and both VDD2 pins; downstream schematics using this part must connect both pins externally and place 0.1 uF bypass capacitors to the corresponding GND side.
Conclusion
The ADN4624BCPZ symbol pin numbers, names, and major footprint characteristics are consistent with the official Analog Devices datasheet for the CP-32-32 LFCSP variant. The only review flags are documentation/semantics: clarify split exposed-pad modeling, optionally rename EPAD pads, and consider clearer ground pin typing. No blocking electrical pinout mismatch was found.

    Sources

    Available Part Information Reviewed

    Key Datasheet Specs

    Pin Cross-Check

    Symbol Pin-Type Cross-Check

    Footprint Cross-Check

    Mismatches / Flags

    Conclusion

Documents

    ADN4624BCPZ Part Review

Assets

kicad_mod

ADN4624BCPZ

CP-32-32_ADI-M.kicad_modFootprint
ADN4624BCPZ-thumb.png

ADN4624BCPZ-thumb.png

ADN4624BCPZ-thumbThumbnail
step

ADN4624BCPZ

CP-32-32_ADI.step3D Model
ADN4624BCPZ

ADN4624BCPZ

ADN4624BCPZ ADN4624BCPZ_0_1 Symbol.svgDefault

ADN4624BCPZ

ADN4624BCPZ thumbnail
LVDS Digital Isolator 5700Vrms 4 Channel 2.5Gbps 40kV/µs CMTI 32-WFQFN Exposed Pad, CSP
The ADN4624 is a quad-channel, signal isolated, low voltage differential signaling (LVDS) buffer that operates at up to 2.5 Gbps with very low jitter. The device integrates Analog Devices, Inc., iCoupler® technology, enhanced for high speed operation to provide drop-in galvanic isolation of LVDS signal chains. AC coupling and/or level shifting to the LVDS receivers and from the LVDS drivers allows isolation of other high speed signals such as current mode logic (CML). The ADN4624 includes a refresh mechanism to monitor the input and output states and ensure they remain the same in the absence of data transitions (for example, at power-on). For lower power consumption and high speed operation with low jitter, the LVDS and isolator circuits rely on 1.8 V supplies. The ADN4624 is fully specified over a wide industrial temperature range and is available in a 28-lead, wide-body, finer pitch SOIC_W_FP package with 8.3 mm creepage and clearance (for 5.7 kV rms or 8 kVPEAK surge and impulse voltages and reinforced insulation at ac mains voltages) or 6 mm × 6 mm LFCSP package with 1.27 mm creepage and clearance (for basic/functional isolation).
FEATURES ► 5.7 kV rms and 1.5 kV rms LVDS isolators ► Complies with TIA/EIA-644-A LVDS signal levels ► Quad-channel configuration ► Any data rate up to 2.5 Gbps switching with low jitter ► 10 Gbps total bandwidth across four channels ► 2.15 ns typical propagation delay ► Typical jitter: 0.82 ps rms random, 40 ps total peak ► Lower power 1.8 V supplies ► ±8 kV IEC 61000-4-2 ESD protection across isolation barrier ► High common-mode transient immunity: 100 kV/μs typical ► Safety and regulatory approvals (28-lead SOIC_W_FP package) ► UL (pending): 5700 V rms for 1 minute per UL 1577 ► CSA Component Acceptance Notice 5A (pending) ► VDE certificate of conformity (pending) ► DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 ► VIORM = 849 VPEAK (working voltage) ► Enable or disable refresh (low speed output correctness check) ► Operating temperature range: −40°C to +125°C ► 28-lead, wide-body, finer pitch SOIC_W_FP package with 8.3 mm creepage and clearance or 6 mm × 6 mm LFCSP package with 1.27 mm creepage and clearance APPLICATIONS ► Isolated video and imaging data ► Analog front-end isolation ► Data plane isolation ► Isolated high speed clock and data links ► Multi-gigabit serialization/deserialization (SERDES) ► Board-to-board optical replacement (for example, short reach fiber)
#CommonPartsLibrary #Isolator #ADN4624BCPZ #AnalogDevices #LVDS #DigitalIsolator #GalvanicIsolation #HighSpeedCommunication #SERDES

Properties

ADN4624BCPZ

Analog Devices Inc.

Isolator

analog.com/media/en/technical-documentation/data-sheets/adn4624.pdf

U

parametric-v1

creativecommons.org/licenses/by/4.0/

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