PCIe differential pairs, REFCLK, PERST# via AC-coupling & chokes
USB2.0 D+/D– from hub to socket
SIM/UIM through ESD array to nano-SIM holder
3.3 V rail and enable/reset to socket and regulator
Review schematic for completeness and electrical requirements
Verify passive/active ratings and footprints
Configure PCB stackup, copper layers, and ground fill
Define mechanical mounting holes and clearance
Perform DRC and length-match checks
Success criteria
The PCIe slot socket is placed but nets aren’t yet routed; supporting I/O, power, SIM, and antenna connectors are pending. Signal-integrity, EMI/ESD compliance, and board-size fit remain to be validated.
Next step
Pick and add the AC-coupling capacitors and common-mode chokes for the PCIe and USB lanes.
Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power
A generic fixed inductor for rapid developing circuit topology. *You can now change the footprint and 3D model at the top level anytime you want. This is the power of #generics