Project Capabilities Overview
2:34
Researching component design advice.
Finding suitable PHYs.
Researching PHY specifications.
Accessing knowledge base.
Running multiple web searches.
Found 10 results.
Found 10 results.
Found 10 results.
Looking for "Summarize key design-relevant features for using DP83867 with an FPGA over RGMII: supported MAC interfaces, RGMII internal delay capability, reference clock options, power rails, reset/strap pins, MDIO/MDC management, and any notes about magnetics or MDI connection." in dp83867ir.pdf
Looking for "Summarize key design-relevant features for using KSZ9031RNX with an FPGA over RGMII: supported MAC interfaces, RGMII internal delay capability, reference clock options, power rails, reset/strap pins, MDIO/MDC management, and any notes about magnetics or MDI connection." in 00002117f.pdf
Looking for "Summarize key design-relevant features for using RTL8211F with an FPGA over RGMII: supported MAC interfaces, RGMII internal delay capability, reference clock options, power rails, reset/strap pins, MDIO/MDC management, and any notes about magnetics or MDI connection." in RTL8211F-CG-Datasheet.pdf
Searching for components.
Finished searching for components.
- Its datasheet explicitly supports RGMII and gives programmable RX/TX clock delay modes with fine adjustment, which makes timing closure much easier than fixed-delay parts.
- It can use a 25 MHz crystal/oscillator and can output a 25 MHz or 125 MHz synchronized clock.
- It has standard MDC/MDIO management, hardware strap pins, and a very clear FPGA-oriented application model.
- KSZ9031RNXCA if you want a very common RGMII PHY. Its datasheet says the PHY adds 1.2 ns typical RX clock delay by default, while TX skew is normally expected from the MAC, with extra pad-skew tuning available.
- RTL8211F-CG if cost matters. Its datasheet provides strap-selectable 2 ns TX and 2 ns RX internal delays, but documentation/integration is usually less pleasant.
- Pick DP83867IRRGZT if this is your first FPGA Ethernet board.
- Pick KSZ9031RNXCA if your FPGA MAC already has good RGMII skew control.
- Pick RTL8211F-CG only if you already know that ecosystem well.
Table
| FPGA MAC | PHY |
|---|---|
| TXC / GTX_CLK | TXC |
| TXD[3:0] | TXD[3:0] |
| TX_CTL | TX_CTL |
| RXC | RXC |
| RXD[3:0] | RXD[3:0] |
| RX_CTL | RX_CTL |
| MDC | MDC |
| MDIO | MDIO |
| RESET output | RESET_N / PHYRSTB |
- Use one skew strategy only: either the MAC inserts clock delay, or the PHY does. Do not add both.
- For DP83867IRRGZT, use the PHY’s programmable RGMII delay unless your FPGA IP requires otherwise.
- For KSZ9031RNXCA, the datasheet default is effectively: PHY handles RX clock skew, MAC handles TX clock skew.
- For RTL8211F-CG, TX/RX delay is set by strap pins.
- Add an MDIO pull-up to the PHY I/O rail.
- KSZ9031RNXCA: datasheet calls for 1.0 kΩ to 4.7 kΩ.
- RTL8211F-CG: datasheet calls for 1.5 kΩ.
- Strap the PHY address and mode pins with external resistors.
- DP83867IRRGZT has internal 9 kΩ ±25% pulldowns and TI recommends 1% external strap resistors.
- Drive reset from the FPGA or a reset supervisor.
- RTL8211F-CG requires reset low for at least 10 ms, then wait 30 ms before register access.
- Add a 25 MHz crystal or oscillator for the PHY.
- If your FPGA MAC wants a reference from the PHY:
- DP83867IRRGZT can provide 25 MHz or 125 MHz clock out.
- KSZ9031RNXCA can output 125 MHz if strapped accordingly.
- RTL8211F-CG can output 125/25 MHz clock.
- The datasheets assume external magnetics between PHY and jack.
- TI specifically recommends a shielded RJ45 and integrated common-mode choke magnetics, and to avoid routing power/ground under the magnetics.
- Keep chassis/shield grounding strategy deliberate near the connector.
- DP83867IRRGZT: needs 2.5 V, 1.0/1.1 V core, plus VDDIO = 3.3/2.5/1.8 V, and has sequencing constraints.
- KSZ9031RNXCA: core rails are 1.2 V, I/O rail 3.3/2.5/1.8 V, and it supports a single-3.3 V design using an on-chip LDO controller with an external FET.
- RTL8211F-CG: uses 3.3 V plus internal/external 1.0 V generation options, and supports RGMII I/O at 3.3/2.5/1.8/1.5 V.
- Keep all RGMII traces short and length-matched within each bus.
- Keep clocks especially clean and avoid stubs.
- Place the PHY close to both the FPGA and the magnetics, but prioritize a clean RGMII escape.
- Keep the MDI differential pairs tightly coupled and routed as controlled-impedance pairs to the magnetics.
- Follow the PHY datasheet guidance for the analog supplies and decoupling islands.
- Use DP83867IRRGZT
- Set RGMII delay in the PHY
- Use MDIO for bring-up
- Add a 25 MHz source, proper straps, magnetics, and RJ45
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