Final Board Check Review
Thought for 4 mins 44 sec
Short answer
- Your sequencer’s flags are open‑drain. With your current wiring, both enable nets are pulled up to VIN through resistors, so yes: if the flags are “cut” (high‑Z/deasserted or IC1 disconnected), both EN pins will sit high.
What’s happening in your design
- IC1 LM3881 flags are open‑drain and need pull‑ups. Per datasheet: the flags are held low until EN is valid, then they “release” high via the pull‑ups (INV tied low = active‑high sequencing).
- U2 path: U2 EN is on Net 8 with R9 to VIN and IC1 FLAG3. When FLAG3 is open (or removed), R9 pulls EN high -> U2 enabled.
- U6 path: U6 EN is on Net 13 with R5 to VIN and IC1 FLAG1/FLAG2. When the flags are open (or removed), R5 pulls EN high -> U6 enabled.
What a pull‑down on U2 EN would do
- Adding a resistor from U2 EN to GND defines a default‑low bias only if it “wins” against any pull‑ups when the flag is open.
- In your current net, the only source for a logic high is the pull‑up ([R9]). IC1’s flag can only pull low; it cannot drive high. So with both a pull‑up and a pull‑down, EN becomes a resistor divider whenever the flag is open. Whether EN reads high or low then depends on the resistor ratio vs. the EN pin VIH/VIL thresholds.
- Practically:
- If you keep [R9] and add a pull‑down, EN will still go high unless the pull‑down is made strong enough to force EN below VIL, which then risks never reaching VIH when the flag releases.
- If you want “default‑off unless the sequencer explicitly enables,” you should either:
- Remove the always‑on pull‑up to VIN and instead have the flag’s pull‑up be the only pull‑up (still tied to a valid rail), sized so that when the flag releases, EN crosses VIH; or
- Insert an active gate (small FET/BJT or logic) so the sequencer actively drives EN high; otherwise, with open‑drain flags, any always‑present pull‑up will make EN high whenever the flag is open.
Datasheet facts supporting this behavior
- LM3881: three open‑drain flags; “pullup resistors should be connected… typical value 100 kΩ.” Flags are held low until EN is valid, then released. With INV low, the outputs behave active‑high (released = high via pull‑up). This means when the flag is open, the net is defined only by your external biasing (pull‑ups/downs).
Next steps
- Do you want the default state (with flags absent/deasserted) to be:
- Default‑ON (both EN high) — keep the pull‑ups ([R9], [R5]) and do not add pull‑downs.
- Default‑OFF (both EN low) — we should either remove the VIN pull‑ups and re‑bias via the sequencer or add proper gating. I can also size a safe pull‑down for U2 after pulling exact VIH/VIL/leakage numbers from the LM27761 datasheet, and do the same for U6.
If you confirm your intended default, I’ll fetch the exact EN thresholds for both parts and propose resistor values or a small gate to guarantee clean logic levels with margin.
Default state choice
Size pulldown resistor
Remove pullups question
Check INV polarity
Add MOSFET gate
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