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design the schmatic and pcb
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I’ll design and verify the full schematic first, then size, place, and route the PCB for simultaneous 12 V/3 A and 5 V/2 A operation from a 20 V/3 A USB-PD source.
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Power Budget
At 20 V input and conservative 90% aggregate buck efficiency: I_IN = 46 W / (20 V × 0.90) = 2.56 A
I completed the engineering brief and power architecture for the 20 V/3 A USB-PD input, 12 V/3 A output, and 5 V/2 A output. No schematic or PCB mutations were possible because the account has no available ACUs.
- Remaining: component selection, schematic capture, ERC, board sizing/stackup, placement, routing, and final DRC.
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Project Specification
Project Overview
Production-intent USB-C PD sink power distribution board. Status: Draft / Design in progress. The board autonomously negotiates a fixed 20 V PDO and generates simultaneous 12 V and 5 V outputs without firmware.
Intended Use
Powered from a standards-compliant USB-C PD source rated at least 60 W. Intended as a compact embedded power module with screw-terminal outputs and common ground.
What the Device Should Do
- Request a fixed 20 V PD PDO autonomously.
- Keep both converters disabled unless a valid 20 V contract is established.
- Supply 12 V at 3 A continuous and 5 V at 2 A continuous simultaneously.
- Protect the input against ESD/transients, overvoltage, overcurrent and hot-plug/inrush stress.
- Provide separate protected outputs and visible power/status indication.
Main Features
- USB-C PD sink input, no firmware required.
- Protected 20 V shared bus.
- Two independent synchronous buck converters.
- Separate 2-position 5.08 mm screw terminals.
- Common ground.
System Architecture
See the dedicated Block Diagram project file. Power flow is USB-C → autonomous PD sink → protected/gated 20 V bus → independent 12 V and 5 V synchronous bucks → protected terminals.
Hardware Subsystems
USB-C / PD
Standalone documented sink controller, preferably STUSB4500 family, configured to request 20 V. CC pins and VBUS sensing/support circuits follow the manufacturer reference design.
Protected 20 V Bus
Low-loss protected path rated above 20 V and 3 A continuous, with OVP/OCP, inrush/hot-plug control where supported, transient suppression, and appropriately rated bulk/ceramic capacitance.
12 V Buck
Synchronous converter, 20 V nominal input, 12 V/3 A continuous output. Datasheet-derived inductor, feedback, bootstrap, compensation and capacitors.
5 V Buck
Independent synchronous converter, 20 V nominal input, 5 V/2 A continuous output. Datasheet-derived inductor, feedback, bootstrap, compensation and capacitors.
Outputs
Separate fused/current-protected rails where practical, discharge/bleeder where needed, rail indicators, and 5.08 mm 2-position terminals.
Interfaces and Connections
- USB-C receptacle: power and CC only; data pins intentionally unused unless required by selected connector/protection arrangement.
- J12V: +12V and GND, 3 A continuous.
- J5V: +5V and GND, 2 A continuous.
Power and Runtime Expectations
Continuous operation at full load from a ≥60 W standards-compliant PD source and cable. No battery or firmware.
Power Tree and Power Budget
Table
| Branch | Output | Efficiency assumption | Estimated 20 V input |
|---|---|---|---|
| 12 V rail | 12 V × 3 A = 36 W | 92% | 36/(20×0.92) = 1.957 A |
| 5 V rail | 5 V × 2 A = 10 W | 90% | 10/(20×0.90) = 0.556 A |
| Total | 46 W | — | 2.513 A |
Allowing controller/indicator loss and margin, shared VBUS connector contacts, protection path, bulk capacitors and PCB copper are designed for at least 3 A continuous, with selected active/protection parts preferably rated ≥4–5 A. A 60 W source at 20 V provides 3 A nominal capacity, leaving roughly 9.7 W between the estimated 50.3 W input and source rating.
Manufacturing and Assembly Expectations
Production-intent SMD power components with real library footprints. Robust through-hole 5.08 mm terminal blocks. Thermal copper and current-path layout are required in the PCB phase.
Firmware-Relevant Hardware Requirements
None. PD negotiation must be autonomous. Any configuration memory must be factory/default-configurable without runtime firmware.
Physical Design Expectations
Connector access at board edges is preferred. High-current loops, switch nodes, feedback networks and decoupling require compact placement during PCB layout.
Important Design Decisions
- Autonomous PD sink controller rather than an MCU/firmware PD stack.
- Both converters gated by validated 20 V contract and protected-path power-good; lower PDOs must not power outputs.
- Independent synchronous bucks to avoid cross-regulation and share thermal load.
Assumptions
- Source and cable support a fixed 20 V PDO at 3 A or more.
- Output loads are continuous and may start simultaneously.
- Common-ground, non-isolated outputs are acceptable.
- Board-size and layer-count constraints are not yet specified; a 4-layer PCB may be recommended for thermal/current performance.
Success Criteria
- Fully populated, wired schematic with real footprints/library parts.
- Verified IC pinouts and datasheet support values.
- 20 V contract condition gates both converters.
- Separate protected 12 V/3 A and 5 V/2 A terminals.
- All unused IC pins explicitly no-connect where appropriate.
- No unresolved critical electrical-rule errors.
Change Notes
- Initial requirements, architecture, assumptions and explicit power budget captured.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
USB-C / PD
Protected 20 V Bus
12 V Buck
5 V Buck
Outputs
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions
Success Criteria
Change Notes
