Smart Running Insole PCB Design

0:00

Work done
  • Renamed the project to insole_master_right.
  • Confirmed the layout shape is 280 mm x 90 mm and the board is still configured as a 2-layer layout.
  • Set/verified manufacturable baseline layout rules: 0.15 mm minimum trace width, 0.15 mm minimum keep out, 0.3 mm minimum hole size, and 0.5 mm board inset margin.
  • Created zone groups for toe, ball, arch, and heel placement planning, and verified key footprints including U1, U2, U4, U5, J1, J3, and J4.
  • Classified routing priorities and verified current DRC/ERC state and BOM readiness.
Success criteria review
  • ✅ Board outline is set to 280 mm x 90 mm.
  • ✅ Placement zones for toe, ball, arch, and heel were defined at the planning/group level.
  • ❌ I could not complete routing of the remaining airwires. The current layout still has 101 airwire errors.
  • ❌ I could not complete the bottom ground plane, antenna keepout, and via stitching implementation.
  • ❌ I could not split and finish the master-right / slave-left deliverables with final silkscreen labels.
  • ❌ Final manufacturability checks do not pass yet: DRC currently reports 101 airwires, 12 overlapping-copper errors, and 89 floating-copper errors.
  • ❌ I did not export Gerbers, BOM deliverables, or render files because export should not be done while the board still fails DRC and has unrouted nets.
Next steps The remaining work is blocked because I cannot continue executing layout-manipulation steps in this session, and the unresolved items require actual PCB editing and routing. The next concrete actions are:
  • route the outstanding nets in priority order: power, ADC, mux, SPI, FSR, then power-management
  • remove/fix the overlapping and floating copper objects
  • add the bottom GND fill with an ESP32 antenna exclusion around U1
  • create the slave-left variant from the current master-right baseline
  • rerun DRC until clean, then export Gerber, BOM, pick-and-place, and render outputs
If you want, I can continue from this exact checkpoint in a new session and drive the remaining validation/export sequence once editing is available again.
7m

Started implementing a plan

## Goal

Create a manufacturable right-foot “master” insole PCB project in Flux EDA (ESP32-S3 + CD74HC4067 FSR mux + Li-ion charging + microSD + connectors), with a long insole form factor and zoning (toe/ball/arch/heel), ready for routing, DRC-clean, and export.

## What’s been completed

- **Project renamed** from placeholder to **`insole_master_right`**.

- **Schematic baseline exists** and was inspected at a high level (179 components, 63 nets). Major parts present: **U1 ESP32-S3-WROOM-1**, **U2 CD74HC4067M**, **U4 AP2112K-3.3TRG1**, **U5 TP4056**, **J1 USB‑C (CUI_UJC-HP-3-SMT-TR footprint)**, **J2 JST-PH 2-pin**, **J3 FFC2B28-16-G**, **J4 microSD (MEM2085-00-115-00-A)**.

- **PCB outline and global rules set**: rectangle **280mm × 90mm**, **cornerRadius=2mm**, **Standard 2 Layer** stackup; rules: **minTraceWidth=0.15mm**, **minKeepOut=0.15mm**, **minHoleSize=0.3mm**, **boardInsetMargin=0.5mm**.

- **Placement zoning started** via a coordinate-based placement pass and grouping into zones:

- `group-toe` (J1)

- `group-ball` (U2 + nearby passives)

- `group-arch` (U1, U4, J4 + caps)

- `group-heel` (U5, J2, J3 + passives)

- **Net-type annotation added** for routing priority (GND/power/analog/low-speed). Note: tool flagged **USB_CC1/USB_CC2 as “high-speed 90Ω”**, which is likely incorrect and needs correction.

- **Current DRC status**: **101 airwires**, **12 overlapping copper**, **89 floating copper**; missing footprints/invalid layer checks pass.

- **Auto-router attempt failed** due to router availability (`unavailable`), so no routing progress was made.

- **Stackup templates availability checked** (standard 1/2/4/6… and JLC/PCBWay 4-layer templates are available), but no stackup change was applied.

## Implementation plan (remaining work only)

1. **Resolve copper geometry errors in the PCB layout** by locating and removing/repairing the sources of **12 overlapping copper** and **89 floating copper** (likely stray pours/shapes). Re-run DRC until overlapping/floating copper errors are cleared.

2. **Verify and finalize placement** by inspecting the baked element positions/orientations for U1/U2/U4/U5/J1/J2/J3/J4 and adjusting placement rules as needed to meet edge clearances and zoning intent.

3. **Implement ESP32-S3 antenna keepout**: obtain the correct board-level element UID for U1 and apply a keepout rule/polygon that blocks copper (top/bottom) under and in front of the antenna region; ensure U1 is at a board edge with antenna facing outward.

4. **Correct net classification/constraints for USB-C CC pins**: set **USB_CC1/USB_CC2** to low/medium-speed (no 90Ω impedance constraint), and ensure CC resistors are treated as short, low-current traces per USB-C sink/UFP practice.

5. **Configure ground strategy for 2-layer**: enable a continuous **bottom-layer GND fill** (with thermal reliefs as appropriate), and maintain the antenna keepout void in the GND pour beneath the ESP32 antenna area.

6. **Complete routing** of all remaining connections (still **101 airwires**) using an available routing approach (manual routing by the human in Flux UI, or switching to a router that is available). Route in order: **VBUS_5V/BAT_PLUS**, **3V3**, **FSR_ADC (analog)**, then remaining digital lines.

7. **Re-run DRC/Electrical checks** after routing and fixes: confirm **0 airwires**, no copper overlap/floating copper, and no ERC power/undriven issues.

8. **BOM readiness pass**: assign real MPN/value/package properties for **Generic Resistor (R1,R2,R5–R8)** and **Generic Capacitor (C1–C13)** so the design is procurement-ready.

9. **Prepare manufacturing export**: once DRC-clean, generate Gerbers/drill and (if assembly) centroid files; add/verify fab notes for board thickness target (≤1.0mm) and edge-routing to the final insole silhouette DXF (if used).

7m

Working on your request...

0:12

6m

inspected layout and review errors

1:32

BOM
PCB Layout
Review (ERC/DRC)
Schematic

Using Knowledge Base Tool.

Using Review (ERC/DRC) Tool.

Using Schematic Tool.

6m

fixing net classes and BOM properties...

4:40

PCB Layout
Review (ERC/DRC)

Using PCB Layout Tool.

Using PCB Layout Tool.

Using PCB Layout Tool.

4m

Set Manufacturer Part Number to "RC0402FR-075K1L" on R1 and R2, Set Manufacturer Name to "YAGEO" on R1, R2, R5, and 3 more, and 15 more changes

0:04

Set R1's Manufacturer Part Number to "RC0402FR-075K1L"

Set R1's Manufacturer Name to "YAGEO"

Set R1's Package or Case Code to "0402"

Set R1's Resistance to "5.1kΩ"

Set R1's Tolerance to "1%"

Set R2's Manufacturer Part Number to "RC0402FR-075K1L"

Set R2's Manufacturer Name to "YAGEO"

Set R2's Package or Case Code to "0402"

Set R2's Resistance to "5.1kΩ"

Set R2's Tolerance to "1%"

Set R5's Manufacturer Part Number to "RC0402FR-071K2L"

Set R5's Manufacturer Name to "YAGEO"

Set R5's Package or Case Code to "0402"

Set R5's Resistance to "1.2kΩ"

Set R5's Tolerance to "1%"

Set R6's Manufacturer Part Number to "RC0402FR-0710KL"

Set R6's Manufacturer Name to "YAGEO"

Set R6's Package or Case Code to "0402"

Set R6's Resistance to "10kΩ"

Set R6's Tolerance to "1%"

Set R7's Manufacturer Part Number to "RC0402FR-0710KL"

Set R7's Manufacturer Name to "YAGEO"

Set R7's Package or Case Code to "0402"

Set R7's Resistance to "10kΩ"

Set R7's Tolerance to "1%"

Set R8's Manufacturer Part Number to "RC0402FR-0710KL"

Set R8's Manufacturer Name to "YAGEO"

Set R8's Package or Case Code to "0402"

Set R8's Resistance to "10kΩ"

Set R8's Tolerance to "1%"

Set C1's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C1's Manufacturer Name to "Samsung Electro-Mechanics"

Set C1's Package or Case Code to "0402"

Set C1's Capacitance to "100nF"

Set C1's Voltage Rating to "16V"

Set C1's Tolerance to "10%"

Set C2's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C2's Manufacturer Name to "Samsung Electro-Mechanics"

Set C2's Package or Case Code to "0402"

Set C2's Capacitance to "100nF"

Set C2's Voltage Rating to "16V"

Set C2's Tolerance to "10%"

Set C3's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C3's Manufacturer Name to "Samsung Electro-Mechanics"

Set C3's Package or Case Code to "0402"

Set C3's Capacitance to "100nF"

Set C3's Voltage Rating to "16V"

Set C3's Tolerance to "10%"

Set C4's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C4's Manufacturer Name to "Samsung Electro-Mechanics"

Set C4's Package or Case Code to "0402"

Set C4's Capacitance to "100nF"

Set C4's Voltage Rating to "16V"

Set C4's Tolerance to "10%"

Set C5's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C5's Manufacturer Name to "Samsung Electro-Mechanics"

Set C5's Package or Case Code to "0402"

Set C5's Capacitance to "100nF"

Set C5's Voltage Rating to "16V"

Set C5's Tolerance to "10%"

Set C6's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C6's Manufacturer Name to "Samsung Electro-Mechanics"

Set C6's Package or Case Code to "0402"

Set C6's Capacitance to "100nF"

Set C6's Voltage Rating to "16V"

Set C6's Tolerance to "10%"

Set C7's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C7's Manufacturer Name to "Samsung Electro-Mechanics"

Set C7's Package or Case Code to "0402"

Set C7's Capacitance to "100nF"

Set C7's Voltage Rating to "16V"

Set C7's Tolerance to "10%"

Set C8's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C8's Manufacturer Name to "Samsung Electro-Mechanics"

Set C8's Package or Case Code to "0402"

Set C8's Capacitance to "100nF"

Set C8's Voltage Rating to "16V"

Set C8's Tolerance to "10%"

Set C9's Manufacturer Part Number to "CL21A106KAYNNNE"

Set C9's Manufacturer Name to "Samsung Electro-Mechanics"

Set C9's Package or Case Code to "0805"

Set C9's Capacitance to "10uF"

Set C9's Voltage Rating to "16V"

Set C9's Tolerance to "10%"

Set C10's Manufacturer Part Number to "CL21A106KAYNNNE"

Set C10's Manufacturer Name to "Samsung Electro-Mechanics"

Set C10's Package or Case Code to "0805"

Set C10's Capacitance to "10uF"

Set C10's Voltage Rating to "16V"

Set C10's Tolerance to "10%"

Set C11's Manufacturer Part Number to "CL21A106KAYNNNE"

Set C11's Manufacturer Name to "Samsung Electro-Mechanics"

Set C11's Package or Case Code to "0805"

Set C11's Capacitance to "10uF"

Set C11's Voltage Rating to "16V"

Set C11's Tolerance to "10%"

Set C12's Manufacturer Part Number to "CL21A106KAYNNNE"

Set C12's Manufacturer Name to "Samsung Electro-Mechanics"

Set C12's Package or Case Code to "0805"

Set C12's Capacitance to "10uF"

Set C12's Voltage Rating to "16V"

Set C12's Tolerance to "10%"

Set C13's Manufacturer Part Number to "CL05B104KO5NNNC"

Set C13's Manufacturer Name to "Samsung Electro-Mechanics"

Set C13's Package or Case Code to "0402"

Set C13's Capacitance to "100nF"

Set C13's Voltage Rating to "16V"

Set C13's Tolerance to "10%"

3m

Set Board Thickness Target to "1.0mm", Set Finish to "ENIG", and 1 more

0:06

Set Board Thickness Target to "1.0mm"

Set Finish to "ENIG"

Set Layout Notes to "Use final right-foot insole silhouette, continuous bottom GND fill except ESP32 antenna keepout, and edge-routed outline for ..."

2m

Updated 1 layout rule

0:03

Set U1's boardInsetMargin to "5mm"

Set U1's protected to "true"

2m

(1 rename skipped due to collision)

⚠️ Rename to 3V3 skipped: designator already exists (kept as Net 1)

1m




  • Ground
    A common return path for electric current. Commonly known as ground.
  • Net Portal
    Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
  • Power Net Portal
    Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power
  • Generic Resistor
    A generic fixed resistor for rapid developing circuit topology. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard resistor values: 1.0Ω 10Ω 100Ω 1.0kΩ 10kΩ 100kΩ 1.0MΩ 1.1Ω 11Ω 110Ω 1.1kΩ 11kΩ 110kΩ 1.1MΩ 1.2Ω 12Ω 120Ω 1.2kΩ 12kΩ 120kΩ 1.2MΩ 1.3Ω 13Ω 130Ω 1.3kΩ 13kΩ 130kΩ 1.3MΩ 1.5Ω 15Ω 150Ω 1.5kΩ 15kΩ 150kΩ 1.5MΩ 1.6Ω 16Ω 160Ω 1.6kΩ 16kΩ 160kΩ 1.6MΩ 1.8Ω 18Ω 180Ω 1.8KΩ 18kΩ 180kΩ 1.8MΩ 2.0Ω 20Ω 200Ω 2.0kΩ 20kΩ 200kΩ 2.0MΩ 2.2Ω 22Ω 220Ω 2.2kΩ 22kΩ 220kΩ 2.2MΩ 2.4Ω 24Ω 240Ω 2.4kΩ 24kΩ 240kΩ 2.4MΩ 2.7Ω 27Ω 270Ω 2.7kΩ 27kΩ 270kΩ 2.7MΩ 3.0Ω 30Ω 300Ω 3.0KΩ 30KΩ 300KΩ 3.0MΩ 3.3Ω 33Ω 330Ω 3.3kΩ 33kΩ 330kΩ 3.3MΩ 3.6Ω 36Ω 360Ω 3.6kΩ 36kΩ 360kΩ 3.6MΩ 3.9Ω 39Ω 390Ω 3.9kΩ 39kΩ 390kΩ 3.9MΩ 4.3Ω 43Ω 430Ω 4.3kΩ 43KΩ 430KΩ 4.3MΩ 4.7Ω 47Ω 470Ω 4.7kΩ 47kΩ 470kΩ 4.7MΩ 5.1Ω 51Ω 510Ω 5.1kΩ 51kΩ 510kΩ 5.1MΩ 5.6Ω 56Ω 560Ω 5.6kΩ 56kΩ 560kΩ 5.6MΩ 6.2Ω 62Ω 620Ω 6.2kΩ 62KΩ 620KΩ 6.2MΩ 6.8Ω 68Ω 680Ω 6.8kΩ 68kΩ 680kΩ 6.8MΩ 7.5Ω 75Ω 750Ω 7.5kΩ 75kΩ 750kΩ 7.5MΩ 8.2Ω 82Ω 820Ω 8.2kΩ 82kΩ 820kΩ 8.2MΩ 9.1Ω 91Ω 910Ω 9.1kΩ 91kΩ 910kΩ 9.1MΩ #generics #CommonPartsLibrary
  • Generic Capacitor
    A generic fixed capacitor ideal for rapid circuit topology development. You can choose between polarized and non-polarized types, its symbol and the footprint will automatically adapt based on your selection. Supported options include standard SMD sizes for ceramic capacitors (e.g., 0402, 0603, 0805), SMD sizes for aluminum electrolytic capacitors, and through-hole footprints for polarized capacitors. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard capacitor values: 1.0pF 10pF 100pF 1000pF 0.01uF 0.1uF 1.0uF 10uF 100uF 1000uF 10,000uF 1.1pF 11pF 110pF 1100pF 1.2pF 12pF 120pF 1200pF 1.3pF 13pF 130pF 1300pF 1.5pF 15pF 150pF 1500pF 0.015uF 0.15uF 1.5uF 15uF 150uF 1500uF 1.6pF 16pF 160pF 1600pF 1.8pF 18pF 180pF 1800pF 2.0pF 20pF 200pF 2000pF 2.2pF 22pF 20pF 2200pF 0.022uF 0.22uF 2.2uF 22uF 220uF 2200uF 2.4pF 24pF 240pF 2400pF 2.7pF 27pF 270pF 2700pF 3.0pF 30pF 300pF 3000pF 3.3pF 33pF 330pF 3300pF 0.033uF 0.33uF 3.3uF 33uF 330uF 3300uF 3.6pF 36pF 360pF 3600pF 3.9pF 39pF 390pF 3900pF 4.3pF 43pF 430pF 4300pF 4.7pF 47pF 470pF 4700pF 0.047uF 0.47uF 4.7uF 47uF 470uF 4700uF 5.1pF 51pF 510pF 5100pF 5.6pF 56pF 560pF 5600pF 6.2pF 62pF 620pF 6200pF 6.8pF 68pF 680pF 6800pF 0.068uF 0.68uF 6.8uF 68uF 680uF 6800uF 7.5pF 75pF 750pF 7500pF 8.2pF 82pF 820pF 8200pF 9.1pF 91pF 910pF 9100pF #generics #CommonPartsLibrary
  • Generic Inductor
    A generic fixed inductor for rapid developing circuit topology. *You can now change the footprint and 3D model at the top level anytime you want. This is the power of #generics
  • Terminal
    Terminal
    An electrical connector acting as reusable interface to a conductor and creating a point where external circuits can be connected.
  • RMCF0805JT47K0
    47 kOhms ±5% 0.125W, 1/8W Chip Resistor 0805 (2012 Metric) Automotive AEC-Q200 Thick Film #forLedBlink
  • 875105359001
    10uF Capacitor Aluminum Polymer 20% 16V SMD 5x5.3mm #forLedBlink #commonpartslibrary #capacitor #aluminumpolymer #radialcan
  • CTL1206FYW1T
    Yellow 595nm LED Indication - Discrete 1.7V 1206 (3216 Metric) #forLedBlink
insole_master_right thumbnail
Bilateral smart running insole data logger using two nearly identical ESP32-S3 pressure-sensing PCBs. Left variant is an ESP-NOW slave without microSD; right variant is the master with microSD logging. Both preserve the 16-zone FSR mux front end, LiPo charging, AP2112K regulation, USB-C charging input, JST battery connector, and the 280mm x 90mm 2-layer low-profile insole form factor.

Properties

Pricing & Availability

Distributor

Qty 1

Arrow

$0.17–$0.47

Digi-Key

$1.81–$3.59

LCSC

$6.74–$6.84

Mouser

$4.24

TME

$3.15

Verical

$1.07–$11.25

Assets

Assets are files uploaded to this project which can be used in various ways.

Controls