I’ll complete the schematic, verify power and connectivity, then proceed through PCB setup, placement, routing, and final DRC checks. I’ll pause only if a physical or safety-critical requirement is genuinely unavailable.
The schematic is complete and electrically clean. I’m moving into PCB setup now, keeping the high-current rectifier/buck section, isolated gate wiring, RF module, and cellular connector physically separated.
The electrical design is finished, but PCB progress is blocked by a layout-stackup persistence fault: the project keeps reverting to two copper layers, and routing preflight is therefore not safe to continue. I’m completing the firmware, bring-up, and compliance documentation while preserving the PCB work already done.
The schematic is complete and ERC-clean, with firmware, bring-up, compliance, safety, and manufacturing files created.
Open blockers
PCB stackup repeatedly reverts to two layers due to a platform persistence fault, so routing cannot safely proceed.
Cellular-area placement remains unroutable.
Production also requires the TVS, cellular connector, fuse-inrush, mounting-hole, and relay-surge items listed in the Manufacturing Readiness Checklist.
The stackup fault has been reported internally; routing and manufacturing export remain intentionally unfinished rather than producing an unsafe board.