Project Start
Worked for 5 mins 56 sec
Created 5 project docs
Firmware Starter — WeLift Gate Controller
Arduino/PlatformIO starter for U3 ESP32-S3-WROOM-1U-N16R8. The mapping below is grounded in the live U3 netlist; TXD0/RXD0 GPIO identities a...
Board Bring-Up Plan — WeLift Gate Controller
Use an isolated, current-limited bench source, DMM, oscilloscope with appropriate differential probing, electronic load, USB data isolator w...
FCC/CE TCF Draft and RF Integration Notes — WeLift Gate Controller
Host controller using U3 ESP32-S3-WROOM-1U-N16R8, a Wi-Fi/Bluetooth module with U.FL external-antenna interface, plus an optional plug-in LT...
Preliminary Safety Analysis and FMEA — WeLift Gate Controller
The product presents only isolated, normally-open dry contacts to command inputs of an independently certified gate operator. It does not sw...
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The schematic is complete and ERC-clean, with firmware, bring-up, compliance, safety, and manufacturing files created.
Open blockers
- PCB stackup repeatedly reverts to two layers due to a platform persistence fault, so routing cannot safely proceed.
- Cellular-area placement remains unroutable.
- Production also requires the TVS, cellular connector, fuse-inrush, mounting-hole, and relay-surge items listed in the Manufacturing Readiness Checklist.
Completed files
The stackup fault has been reported internally; routing and manufacturing export remain intentionally unfinished rather than producing an unsafe board.
Fix blockers and review
Fix PCB blockers
Replace input TVS
Verify cellular connector
Review BOM cost
Refine this doc
Ask about this doc
Board Bring-Up Plan — WeLift Gate Controller
Safety and equipment
Use an isolated, current-limited bench source, DMM, oscilloscope with appropriate differential probing, electronic load, USB data isolator where required, and only a dry-contact test fixture. Do not connect a gate or motor during bring-up. The 12–24 VAC/DC input is SELV in intended use, but rectified nodes and stored energy still require controlled handling.
Exact power path and test points
J1 FIELD_IN_A/FIELD_IN_B → F1 2 A → D1 prototype TVS → BR1 GBU8K → VRECT (C1+C2 4700 µF each) → U1 LM5013 → 5V → U2 TLV62568 → 3V3. 5V → U4 MP5077 → CELL_5V_SW/J7. 5V → U7 B0505S → ISO_5V/ISO_GND. Relays K1/K2 use 5 V coils. U3 uses 3V3.0. Pre-power inspection — PASS required
- Confirm orientation/polarity of F1, D1, BR1, C1/C2, U1/U2/U4/U7, D2/D3/D5 and LEDs; inspect QFN/PowerSOIC exposed pads.
- Measure no short: VRECT–GND, 5V–GND, 3V3–GND, CELL_5V_SW–GND, ISO_5V–ISO_GND. Fail: stable resistance below 10 Ω after capacitors charge, or diode-mode hard short.
- Verify relay COM/NO nets have >10 MΩ to GND, 5V, 3V3 and ISO_GND with relays off.
- D1 is prototype-only: do not apply 24 VAC high line until replaced by a qualified 40–43 V bidirectional ≥600 W TVS or temporarily removed under controlled lab conditions.
1. Low-voltage DC first power
- Disconnect J7 modem and all field terminals. Set source to 12.0 VDC, 0.10 A limit; feed J1 in either polarity.
- If current limit is hit for >100 ms, power down and inspect. Otherwise raise limit to 0.50 A, then 1.0 A after rails are confirmed.
- Measure BR1 output
VRECT: PASS 10.5–12.0 VDC at light load (allow bridge drop); no reversed electrolytic voltage. - Measure
5V: PASS 4.85–5.15 V steady. Measure3V3: PASS 3.20–3.40 V.CELL_5V_SWmust be 15 °C rapid temperature rise during a 5-minute light-load run.
3. Ripple and load regulation
- Probe with short ground spring at C6/C7 (
5V) and C9/C10/C11 (3V3). Bandwidth-limit to 20 MHz and record both broadband and switching ripple. - 5V load points: 0.1 A, 1.0 A, 2.0 A, and short 3.26 A system-equivalent peaks. PASS: 4.75–5.25 V, ripple ≤150 mVpp steady and transient undershoot ≥4.60 V for 10 MΩ**.
- Command 0.75 s pulses separately. PASS: selected COM–NO 10 MΩ within 2.0 s; the other relay never closes.
- Attempt simultaneous/repeated commands. PASS: firmware interlock prevents overlap; absolute activation never exceeds 2.5 s even on malformed input.
- Do not perform contact voltage/current or surge testing until gate-operator interface limits are supplied.
6. Isolated position inputs
- Verify
ISO_5Vis 4.75–5.25 V referenced to ISO_GND and isolation resistance from ISO_GND to GND is >10 MΩ unpowered. - J4 is OPEN status; J5 is CLOSED status. Use only a floating switch/jumper—never inject external voltage.
- Open contact: GPIO7/GPIO8 net should be >2.8 V and reported inactive. Closed contact: corresponding net should be <0.8 V and reported active.
- Toggle each contact with contact bounce. PASS: reported state changes once after 40 ms debounce; no cross-channel changes. Both-active state must be reported as diagnostically invalid by production firmware, not used to initiate motion.
7. Cellular rail and load-pulse test
- Keep J7 modem absent initially. Enable GPIO9;
CELL_5V_SWshall ramp to 4.75–5.25 V. Disable it; fall below 0.5 V within a recorded safe discharge time. - Apply electronic load at J7 pins 1–2 versus 3–4: 0.4 A continuous plus 2.0 A pulses (start 100 ms, 10% duty; extend per selected module profile). PASS: CELL_5V_SW ≥4.60 V, 5V ≥4.60 V, 3V3 ≥3.0 V, no U3 reset, U4 current limit approximately 2.28 A behaves without oscillation, connector/pins rise <20 °C after 10 minutes.
- Verify UART: U3 GPIO43 TX → J7-6, J7-5 → GPIO44 RX, RTS GPIO15/J7-8, CTS GPIO16/J7-7. Verify J7-9 GPIO17 and J7-10 GPIO18 only after module selection.
- Final modem boot, reset timing, baud and AT-command pass/fail criteria are module-dependent TODOs.
8. Fuse/inrush and thermal validation
- Capture J1 inrush at 12/24 VDC and 12/24 VAC, cold and hot, including 9400 µF reservoir charging and cellular pulses.
- PASS: F1 0451002.MRL does not nuisance-open over 50 cold starts and 50 hot starts at each source condition; peak/RMS remain inside manufacturer time-current limits with margin. Otherwise qualify a time-delay 2.5 A correction only after connector/copper/source review.
- Run worst credible load for 1 hour at room ambient; no component may exceed its rating. Production thermal pass limits require enclosure ambient and derating definition.
Stop conditions
Any relay closure during reset/communications loss, 5V <4.60 V, 3V3 <3.0 V, fuse operation, D1 heating at normal input, isolation breakdown, smoke/odor, or uncontrolled modem-rail cycling is an immediate FAIL and design-review stop.
Safety and equipment
Exact power path and test points
0. Pre-power inspection — PASS required
1. Low-voltage DC first power
2. AC/DC input envelope and rectifier tests
3. Ripple and load regulation
4. ESP32-S3 native USB and boot/reset
5. Relay dry-contact verification — no gate connected
6. Isolated position inputs
7. Cellular rail and load-pulse test
8. Fuse/inrush and thermal validation
Stop conditions
