Verilog
module i2c_slave(
    input clk,
    input rst,
    inout sda,
    input scl,
    input sda_temp,       // external (open-drain pullup) signal on sda
    output reg wr_en,
    output reg rd_en,
    output reg [7:0] data_in,
    input  [7:0] data_out,
    output reg [7:0] addr,
    output reg start,
    output reg stop
);

  // Internal signals
  reg enable;
  reg r_w;
  reg [3:0] cnt_byte;    // counter for bits in a byte (counts 0 to 8)
  reg [6:0] slave_addr;  // 7-bit slave address received from master
  reg [7:0] reg_addr;    // 8-bit register address (to select regA or regB)
  reg sda_out, sda_ack, sda_assign;
  
  // State machine declaration
  typedef enum reg [2:0] {
    IDLE          = 3'b000,
    SLAVE_ADDR_READ = 3'b001,  // Receive slave address (7-bit) + R/W bit
    ACK_SLAVE     = 3'b010,  // Acknowledge slave address reception
    REGADDR_READ  = 3'b011,  // Receive full 8-bit register address
    ACK_REG       = 3'b100,  // Acknowledge register address reception
    RW_CHECK      = 3'b101,  // (Optional) Check r/w bit (here merged in next state)
    ACK           = 3'b110,  // Acknowledge before data phase
    DATA          = 3'b111   // Data transfer phase
  } state_t;
  
  state_t state, next_state;
  
  // Generate start condition: when sda falls with scl high
  always @(negedge sda or posedge rst) begin
    if (rst)
      start = 1 && cnt_byte = 1 && cnt_byte = ACK_REG)
        addr = reg_addr;
      else
        addr = addr;
    end
  end

  // Next state and ACK generation logic
  always @(posedge scl or posedge rst) begin
    if (rst) begin
      next_state  this forms the MSB of 8: 0001000
    @(posedge clk); scl = 0;
    // Bit 3:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0
    @(posedge clk); scl = 0;
    // Bit 2:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0
    @(posedge clk); scl = 0;
    // Bit 1:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0
    @(posedge clk); scl = 0;
    // Bit 0 (R/W bit):
    @(posedge clk); scl = 1; sda_temp = 0;  // 0 for write
    @(posedge clk); scl = 0;

    // (Simulate slave ACK here by letting slave drive sda; no action required from master)

    @(posedge clk);

    // --- Transmit register address byte (for example, 8'd5) ---
    // 8'd5 = 00000101
    // Bit 7:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0
    @(posedge clk); scl = 0;
    // Bit 6:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0
    @(posedge clk); scl = 0;
    // Bit 5:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0
    @(posedge clk); scl = 0;
    // Bit 4:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0
    @(posedge clk); scl = 0;
    // Bit 3:
    @(posedge clk); scl = 1; sda_temp = 1;  // 1 (value 4)
    @(posedge clk); scl = 0;
    // Bit 2:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0
    @(posedge clk); scl = 0;
    // Bit 1:
    @(posedge clk); scl = 1; sda_temp = 1;  // 1 (value 2)
    @(posedge clk); scl = 0;
    // Bit 0:
    @(posedge clk); scl = 1; sda_temp = 0;  // 0 (value 1 is 0)
    @(posedge clk); scl = 0;

    // (Simulate slave ACK for register address)
    @(posedge clk);

    // --- Transmit data byte to write into the selected register ---
    // For example, data = 8'd55; 55 = 00110111
    // Bit 7:
    @(posedge clk); scl = 1; sda_temp = 0;
    @(posedge clk); scl = 0;
    // Bit 6:
    @(posedge clk); scl = 1; sda_temp = 0;
    @(posedge clk); scl = 0;
    // Bit 5:
    @(posedge clk); scl = 1; sda_temp = 1;
    @(posedge clk); scl = 0;
    // Bit 4:
    @(posedge clk); scl = 1; sda_temp = 1;
    @(posedge clk); scl = 0;
    // Bit 3:
    @(posedge clk); scl = 1; sda_temp = 0;
    @(posedge clk); scl = 0;
    // Bit 2:
    @(posedge clk); scl = 1; sda_temp = 1;
    @(posedge clk); scl = 0;
    // Bit 1:
    @(posedge clk); scl = 1; sda_temp = 1;
    @(posedge clk); scl = 0;
    // Bit 0:
    @(posedge clk); scl = 1; sda_temp = 1;
    @(posedge clk); scl = 0;

    // (Simulate slave ACK for data byte)
    @(posedge clk);

    // --- Generate stop condition ---
    sda_temp = 1; stop = 1;
    @(posedge clk); scl = 1; stop = 0;
    repeat(2) @(posedge clk);

    $finish;
  end
endmodule

1. The slave now first captures an 8‑bit byte (7-bit slave address + R/W) in the state SLAVE_ADDR_READ and issues an ACK (ACK_SLAVE).
2. Next, it captures the 8‑bit register address in REGADDR_READ with an ACK (ACK_REG).
3. It then continues into the data phase (state DATA), where data is either received (write) or transmitted (read) based on the R/W flag.
4. The testbench sends first the slave address byte, then the register address, followed by a data byte, and finally a stop condition.