• [4-layer] OSHPARK Constraints

    [4-layer] OSHPARK Constraints

    Use this template if you're planning to get your board manufactured in OSHPARK. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules OSHpark 4-layer stackup specs: Top overlay or silkscreen: 1 mil thick Top solder mask or solder resist: 1 mil thick Top copper: 1.7 mil thick on 1 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Mid layer 1: 0.68 mil thick on 0.5 oz copper Dielectric core: 39 mil thick FR408HR Mid layer 2: 0.68 mil thick on 0.5 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Bottom copper: 1.7 mil thick on 1 oz copper Bottom solder mask or solder resist: 1 mil thick
Bottom overlay or silkscreen: 1 mil thick

    jharwinbarrozo

    2 years ago

    0 Uses

    5 Comments

    5 Stars


  • Group 17 LED Connector

    Group 17 LED Connector

    Welcome to your new project. Imagine what you can build here.

    4 years ago

    0 Uses

    1 Comment

    0 Stars


  • Group 17 LED Connector

    Group 17 LED Connector

    Welcome to your new project. Imagine what you can build here.

    4 years ago

    0 Uses

    1 Comment

    0 Stars


  • [4-layer] OSHPARK Constraints ayg8

    [4-layer] OSHPARK Constraints ayg8

    Use this template if you're planning to get your board manufactured in OSHPARK. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules OSHpark 4-layer stackup specs: Top overlay or silkscreen: 1 mil thick Top solder mask or solder resist: 1 mil thick Top copper: 1.7 mil thick on 1 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Mid layer 1: 0.68 mil thick on 0.5 oz copper Dielectric core: 39 mil thick FR408HR Mid layer 2: 0.68 mil thick on 0.5 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Bottom copper: 1.7 mil thick on 1 oz copper Bottom solder mask or solder resist: 1 mil thick
Bottom overlay or silkscreen: 1 mil thick

    2 years ago

    0 Uses

    5 Comments

    0 Stars


  • [4-layer] OSHPARK Constraints

    [4-layer] OSHPARK Constraints

    Use this template if you're planning to get your board manufactured in OSHPARK. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules OSHpark 4-layer stackup specs: Top overlay or silkscreen: 1 mil thick Top solder mask or solder resist: 1 mil thick Top copper: 1.7 mil thick on 1 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Mid layer 1: 0.68 mil thick on 0.5 oz copper Dielectric core: 39 mil thick FR408HR Mid layer 2: 0.68 mil thick on 0.5 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Bottom copper: 1.7 mil thick on 1 oz copper Bottom solder mask or solder resist: 1 mil thick
Bottom overlay or silkscreen: 1 mil thick

    2 years ago

    0 Uses

    1 Comment

    0 Stars


  • FDB1D7N10CL7 4d05

    FDB1D7N10CL7 4d05

    The FDB1D7N10CL7 is an N-Channel Shielded Gate POWERTRENCH® MOSFET manufactured by ON Semiconductor. This advanced MOSFET leverages ON Semiconductor's POWERTRENCH process, incorporating Shielded Gate technology to deliver minimized on-state resistance and superior switching performance with a high-quality soft body diode. The component features a maximum drain-to-source voltage (VDS) of 100 V and can handle continuous drain currents up to 268 A at 25°C. It boasts a low RDS(on) value of 1.7 mΩ at a gate-to-source voltage (VGS) of 12 V and drain current (ID) of 100 A, making it highly efficient for power management applications. Key applications include industrial motor drives, power supplies, automation, battery-operated tools, solar inverters, and energy storage systems. The FDB1D7N10CL7 is housed in a robust D2PAK7 (TO-263 7 LD) package and is designed to withstand a wide range of operating temperatures from -55°C to +175°C.

    2 years ago

    0 Uses

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    0 Stars


  • [4-layer] OSHPARK Constraints - Midas

    [4-layer] OSHPARK Constraints - Midas

    Use this template if you're planning to get your board manufactured in OSHPARK. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules OSHpark 4-layer stackup specs: Top overlay or silkscreen: 1 mil thick Top solder mask or solder resist: 1 mil thick Top copper: 1.7 mil thick on 1 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Mid layer 1: 0.68 mil thick on 0.5 oz copper Dielectric core: 39 mil thick FR408HR Mid layer 2: 0.68 mil thick on 0.5 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Bottom copper: 1.7 mil thick on 1 oz copper Bottom solder mask or solder resist: 1 mil thick
Bottom overlay or silkscreen: 1 mil thick

    3 years ago

    0 Uses

    0 Comments

    0 Stars


  • IPB017N10N5LF bbc8

    IPB017N10N5LF bbc8

    The IPB017N10N5LF is a high-performance N-channel MOSFET from Infineon's OptiMOS™ 5 Linear FET series, designed specifically for hot-swap and e-fuse applications. This 100 V component, housed in a D2-PAK 7pin package (PG-TO 263-7), features exceptionally low on-resistance (RDS(on)) and a wide safe operating area (SOA), making it ideal for demanding power management tasks. The device is rated for a continuous drain current of up to 180 A (silicon limited) and 314 A (package limited), with a maximum pulsed drain current of 720 A. It supports gate-source voltages ranging from -20 V to 20 V and is 100% avalanche tested, ensuring robust performance under extreme conditions. The IPB017N10N5LF is RoHS compliant, Pb-free, and halogen-free, adhering to environmental standards. Key electrical characteristics include a maximum RDS(on) of 1.7 mΩ at VGS=10 V and a gate threshold voltage range of 2.5 V to 4.1 V. This MOSFET is suitable for applications requiring high efficiency and reliability, supported by its qualification according to JEDEC standards.

    2 years ago

    0 Uses

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    0 Stars


  • [4-layer] OSHPARK Constraints 0dcb

    [4-layer] OSHPARK Constraints 0dcb

    Use this template if you're planning to get your board manufactured in OSHPARK. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules OSHpark 4-layer stackup specs: Top overlay or silkscreen: 1 mil thick Top solder mask or solder resist: 1 mil thick Top copper: 1.7 mil thick on 1 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Mid layer 1: 0.68 mil thick on 0.5 oz copper Dielectric core: 39 mil thick FR408HR Mid layer 2: 0.68 mil thick on 0.5 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Bottom copper: 1.7 mil thick on 1 oz copper Bottom solder mask or solder resist: 1 mil thick
Bottom overlay or silkscreen: 1 mil thick

    3 years ago

    0 Uses

    0 Comments

    0 Stars


  • [4-layer] OSHPARK Constraints

    [4-layer] OSHPARK Constraints

    Use this template if you're planning to get your board manufactured in OSHPARK. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules OSHpark 4-layer stackup specs: Top overlay or silkscreen: 1 mil thick Top solder mask or solder resist: 1 mil thick Top copper: 1.7 mil thick on 1 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Mid layer 1: 0.68 mil thick on 0.5 oz copper Dielectric core: 39 mil thick FR408HR Mid layer 2: 0.68 mil thick on 0.5 oz copper Dielectric: 7.96 mil thick FR408HG 2113 Bottom copper: 1.7 mil thick on 1 oz copper Bottom solder mask or solder resist: 1 mil thick
Bottom overlay or silkscreen: 1 mil thick

    2 years ago

    0 Uses

    0 Comments

    0 Stars