FPGA Pin Audit


Check this schematic component against the datasheet for [MPN] and assign the correct pin orientation, section, and terminal order without changing, replacing, renumbering, or remapping any pins. Remove the Pin Group property from all pins if it exists. Place Power pins first and Ground pins last. Within each section, distribute the pins as evenly as possible between the left and right sides; for example, split 10 pins as 5/5 and 11 pins as 5/6 or 6/5. If a section contains only one pin, leave it on the most appropriate side. Keep the symbol compact, balanced, and visually symmetrical. If a pin function is unclear, assign Unclear / Check datasheet, then apply all changes directly to the schematic component.
I’ll use the current part MPN, XC7A50T-L2CPG236E, and apply a datasheet-grounded symbol organization: power first, functional bank/configuration sections next, ground last, balanced left/right pin placement, terminal ordering, and removal of all Pin Group properties—without changing any pin identity or ball mapping.
The authoritative 238-terminal snapshot is complete and confirms CPG236 legitimately uses 238 physical terminals. The first write pass was safely aborted before any partial edits; I’m retrying with bounded functional batches so the original pin mapping remains protected.
Updated the XC7A50T-L2CPG236E symbol using AMD documentation: all 238 pins retain their original names and ball mappings, now organized into power, configuration/JTAG, XADC, GTP, I/O-bank, and ground sections. Terminal orders are unique from 1–238, Pin Group was removed from every pin, and each section is balanced across left/right orientations; no unclear pins remained.
Open item:
  • Existing pin electrical types remain Unspecified, as requested—no pin types or mappings were changed.
Fix part metadata
Set electrical pin types
Add official datasheet
Audit footprint geometry

GND_1
Pin Number
A1
MGTPTXN1_216
Pin Number
A2
GND_2
Pin Number
A3
Name
Pin #
Type
Part Type
Pin Orientation
Section
Terminal Order
GND_1
A1
Unspecified
Terminal
Left
10 Ground
186
MGTPTXN1_216
A2
Unspecified
Terminal
Right
04 GTP Bank 216
74
GND_2
A3
Unspecified
Terminal
Right
10 Ground
187
MGTPRXN0_216
A4
Unspecified
Terminal
Left
04 GTP Bank 216
68
GND_3
A5
Unspecified
Terminal
Left
10 Ground
188
MGTPRXN1_216
A6
Unspecified
Terminal
Right
04 GTP Bank 216
70
GND_4
A7
Unspecified
Terminal
Right
10 Ground
189
MGTREFCLK0N_216
A8
Unspecified
Terminal
Left
04 GTP Bank 216
76
GND_5
A9
Unspecified
Terminal
Left
10 Ground
190
MGTREFCLK1N_216
A10
Unspecified
Terminal
Right
04 GTP Bank 216
78
DXP_0
A11
Unspecified
Terminal
Left
03 XADC and Analog
65
VP_0
A12
Unspecified
Terminal
Left
03 XADC and Analog
61
VREFN_0
A13
Unspecified
Terminal
Right
03 XADC and Analog
64
IO_L6P_T0_16
A14
Unspecified
Terminal
Left
06 I/O Bank 16
130
IO_L6N_T0_VREF_16
A15
Unspecified
Terminal
Left
06 I/O Bank 16
131
IO_L12P_T1_MRCC_16
A16
Unspecified
Terminal
Left
06 I/O Bank 16
134
IO_L12N_T1_MRCC_16
A17
Unspecified
Terminal
Left
06 I/O Bank 16
135
IO_L19N_T3_VREF_16
A18
Unspecified
Terminal
Right
06 I/O Bank 16
141

XC7A50T-L2CPG236E

XC7A50T-L2CPG236E thumbnail