Datasheet Pin Grouping
Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.
Thought for 6 sec
I’ll assign terminal order/orientation by the current generalized pin groups, with Power at order 1/top and Ground at order 10/bottom, then verify the properties.
Worked for 1 min 27 sec
Assigned Terminal Order and Pin Orientation across all pins and verified the updates.
Open items:
- There are more groups than available non-power/non-ground side orientations, so Left/Right orientations are necessarily reused across groups.
Suggested next steps:
- Review the symbol rendering to confirm the layout reads well.
- If you want, I can rebalance individual pins within Address/Data/Control for a cleaner visual symbol.
Rebalance, review and update
Rebalance symbol visually
Fix metadata notes
Run review checks
Update review report
Name
Pin #
Type
Part Type
Pin Description
Pin Group
VDD_1
1
Power In
Terminal
VDD core power for input buffers and internal logic circuit inside DRAM.
Power
DQ0
2
Bi-Directional
Terminal
Data input/output pin; multiplexed for data output and input.
Data Bus
VDDQ_1
3
Power In
Terminal
VDDQ separated I/O buffer power supply to improve DQ noise immunity.
Power
DQ1
4
Bi-Directional
Terminal
Data input/output pin; multiplexed for data output and input.
Data Bus
DQ2
5
Bi-Directional
Terminal
Data input/output pin; multiplexed for data output and input.
Data Bus
VSSQ_1
6
Ground
Terminal
VSSQ separated I/O buffer ground to improve DQ noise immunity.
Ground
DQ3
7
Bi-Directional
Terminal
Data input/output pin; multiplexed for data output and input.
Data Bus
DQ4
8
Bi-Directional
Terminal
Data input/output pin; multiplexed for data output and input.
Data Bus
VDDQ_2
9
Power In
Terminal
VDDQ separated I/O buffer power supply to improve DQ noise immunity.
Power
DQ5
10
Bi-Directional
Terminal
Data input/output pin; multiplexed for data output and input.
Data Bus
DQ6
11
Bi-Directional
Terminal
Data input/output pin; multiplexed for data output and input.
Data Bus
VSSQ_2
12
Ground
Terminal
VSSQ separated I/O buffer ground to improve DQ noise immunity.
Ground
DQ7
13
Bi-Directional
Terminal
Data input/output pin; multiplexed for data output and input.
Data Bus
VDD_2
14
Power In
Terminal
VDD core power for input buffers and internal logic circuit inside DRAM.
Power
LDQM
15
Input
Terminal
Lower byte data mask; high masks lower data during write and places output buffer Hi-Z during read after latency.
Data Bus
~WE
16
Input
Terminal
Active-low write enable command input; sampled with RAS and CAS at CLK rising edge.
Control Bus
~CAS
17
Input
Terminal
Active-low column address strobe command input; sampled with RAS and WE at CLK rising edge.
Control Bus
~RAS
18
Input
Terminal
Active-low row address strobe command input; sampled with CAS and WE at CLK rising edge.
Control Bus
W9825G6KH-5I
