Part Audit Review

Thought for 1 min 58 sec
Thought for 6 sec
Referenced guidance.
1/4 Inspect latest symbol and footprint state

Inspect latest symbol and footprint state

Rebuild the symbol with 10 exact logical terminals

Repair split-pad mapping without changing land geometry

Verify pin names, types, descriptions, numbering, and footprint geometry

Thought for 18 sec — Figuring out orchestration schema
Thought for 9 sec
Awaiting 1 background task
Received notification from "TPS259470LRPWR Symbol Repair" that it finished — picking the work back up.

flux

I’m reconciling the executor’s edits now; the pin metadata and duplicate numbering landed, but I’m checking the reported platform limitation around hiding split-pad segments from the logical symbol.

flux

The exact pin names, types, descriptions, groups, and orientations are populated for pins 1–10. I restored unique numbering for the four split-land terminals and reapplied the original RPW0010A geometry after duplicate numbering disrupted footprint generation.
  • Blocked: Flux currently cannot map multiple copper primitives to one logical terminal while hiding the extra terminals from the parametric symbol. The safe state remains 14 terminals/pads; forcing 10 logical terminals corrupts the footprint.
  • I submitted this platform limitation to the engineering team.
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Files

Pins

Symbol

Layout

Preview

ITIMER
Pin Number
10
DVDT
Pin Number
7
~FLT
Pin Number
4
AUXOFF
Pin Number
3
ITIMER_2
Pin Number
11
PGTH/~FLT_2
Pin Number
13
OUT
Pin Number
6
DVDT_2
Pin Number
14
EN/UVLO_2
Pin Number
12
IN
Pin Number
5
GND
Pin Number
8
ILM
Pin Number
9
OVLO
Pin Number
2
EN/UVLO
Pin Number
1
Part Audit Report
Scope
Audit of TPS259470LRPWR metadata, schematic symbol, terminal definitions, and RPW0010A footprint against the official Texas Instruments TPS25947xx datasheet, Rev. C (SLVSFC9C, revised May 2026).
Official datasheet: https://www.ti.com/lit/ds/symlink/tps25947.pdf
Metadata review

Table

FieldCurrent valueDatasheet / manufacturer valueResult
Manufacturer part numberTPS259470LRPWRTPS259470LRPWRMatch
ManufacturerTexas InstrumentsTexas InstrumentsMatch
Description2.7–23 V, 5.5 A, 28 m true reverse-current-blocking eFuse with input reverse-polarity protection2.7–23 V, 5.5 A, 28 mΩ true reverse-current-blocking eFuse with input reverse-polarity protectionFunctionally correct; missing Ω in the displayed resistance value
Package10-VQFN-HR (2 × 2), RPWVQFN-HR, RPW0010A, 10 pins, nominal 2 mm × 2 mm, 1 mm maximum heightMatch
Pin countPart currently exposes 14 terminalsDevice has 10 logical pinsMismatch
MountReverseSurface-mount VQFN-HRMismatch; “Reverse” is not the correct mounting classification
Part TypeBlankeFuse / electronic fuse / power-management ICMissing
Datasheet URLExisting uploaded PDF URLOfficial TI URL abovePresent, so it was not overwritten. The attached document content matches the official TPS25947 Rev. C datasheet queried during this audit.
Correct pinout for TPS259470L

Table

PinCorrect nameTypeRequired description
1EN/UVLOAnalog inputActive-high enable and adjustable undervoltage-lockout input; must not float
2OVLOAnalog inputAdjustable overvoltage-lockout input and active-low enable; must not float
3AUXOFFOpen-drain digital outputAuxiliary-channel control output for priority power-MUX applications
4FLTOpen-drain digital outputActive-low fault indicator
5INPowerPower input
6OUTPowerPower output
7DVDTAnalog outputExternal capacitor sets output turn-on slew rate; may be left open for fastest turn-on
8GNDGroundGround reference for internal circuitry
9ILMAnalog outputCurrent-limit programming and load-current monitor; must not float
10ITIMERAnalog outputOvercurrent blanking timer capacitor; may be left open for fastest response
Symbol findings
The symbol is not datasheet-correct:
  • It contains 14 logical pins rather than 10.
  • Four physical land-pattern segments were incorrectly promoted to additional logical symbol pins:
    • EN/UVLO_2 is numbered 12 but should be another copper segment belonging to logical pin 1.
    • PGTH/~FLT_2 is numbered 13 but should belong to logical pin 4.
    • DVDT_2 is numbered 14 but should belong to logical pin 7.
    • ITIMER_2 is numbered 11 but should belong to logical pin 10.
  • All symbol pin electrical types are Unspecified and pin descriptions are absent.
  • Variant-generic names are used where this exact orderable part requires variant-specific names:
    • Pin 2 should be OVLO, not OVLO/OVCSEL.
    • Pin 3 should be AUXOFF, not PG/AUXOFF.
    • Pin 4 should be FLT, not PGTH/FLT.
  • Power pins are named VIN and VOUT; TI names them IN and OUT. This is understandable but not an exact datasheet match.
Footprint findings
The footprint geometry is consistent with TI’s RPW0010A recommended land pattern:
  • Nominal package: 2 mm × 2 mm VQFN-HR.
  • Long central pads for pins 5 and 6 are 0.30 mm × 2.40 mm.
  • Side pads use 0.25/0.30 mm widths and 0.60 mm lengths as shown in the TI land pattern.
  • Corner split segments and their approximately ±0.725 mm / ±1.025 mm positions align with the recommended geometry.
The footprint’s copper geometry appears correct, but its terminal mapping is not. The four split physical pads must reuse logical pin numbers 1, 4, 7, and 10 rather than creating logical pins 12, 13, 14, and 11. The finished part should expose 10 logical terminals while retaining all 14 copper pad primitives.
Key specifications
  • Operating input voltage: 2.7 V to 23 V.
  • Absolute-maximum input voltage: 28 V.
  • Negative input withstand: down to −15 V, subject to the VIN/VOUT differential limit.
  • Continuous switch current: 5.5 A maximum with TJ ≤ 125°C.
  • Integrated back-to-back FET on-resistance: 28.2 mΩ typical at VIN = 12 V, IOUT = 3 A, TJ = 25°C; 45 mΩ maximum across the stated operating range.
  • True reverse-current blocking with input reverse-polarity protection.
  • Adjustable overvoltage lockout and active current limiting.
  • TPS259470L fault response: latch-off.
  • AUXOFF and active-low FLT open-drain outputs.
  • Junction temperature range: −40°C to 125°C.
  • Package thermal resistance RθJA: 41.7°C/W on TI’s custom four-layer board with eight thermal vias; 74.5°C/W on the referenced JEDEC board without thermal vias.
  • Orderable package: RPW VQFN-HR, 10 pins, 2 mm × 2 mm, tape-and-reel quantity 3000.
  1. Rebuild the symbol as 10 logical pins.
  2. Map the 14 footprint copper primitives to pin numbers 1–10, duplicating pin numbers 1, 4, 7, and 10 on their split pad segments.
  3. Change exact-variant pin names to OVLO, AUXOFF, and FLT.
  4. Populate pin types and descriptions from the pin table above.
  5. Set Mount to SMD / Surface Mount.
  6. Set Part Type to eFuse or the closest supported electronic-fuse/power-management category.
  7. Optionally replace the uploaded datasheet URL with TI’s stable official URL for provenance, although the existing Datasheet property is already populated and was therefore left unchanged per the request.

  • Scope

  • Metadata review

  • Correct pinout for TPS259470L

  • Symbol findings

  • Footprint findings

  • Key specifications

  • Recommended corrections