STM32H573VIT7 Audit
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Make the functional group more general.
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Add a Section property to all pins, and apply the same value used in the Pin Group property to each pin's Section property.
Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.
Thought for 13 sec
I’ll consolidate the pins into four general, exclusive groups—Power, GPIO, Clock / Control, and Ground—then apply matching Section values, group-level Terminal Orders, and one distinct orientation per group.
Worked for 2 mins 10 sec
The grouping is consolidated into four general sections. I’m verifying representative pins from each group and the requested order/orientation values.
Thought for 24 sec
Updated and verified all 100 pins:
- Power: Order 1, Top
- GPIO: Order 4, Left
- Clock / Control: Order 7, Right
- Ground: Order 10, Bottom
Every pin now has matching
Pin Group and Section values and belongs to exactly one group. Pin numbers, names, positions, and footprint mappings remain unchanged.Fix metadata and pins
Add pin descriptions
Review symbol rendering
Update audit report
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STM32H573VIT7 Part Audit
Result
The part was audited against STMicroelectronics datasheet DS14121 Rev. 5 (May 2025) and ST's official STM32 open-pin database. The existing Datasheet URL is already an official ST URL, so no property update was required.
- Official datasheet: https://www.st.com/resource/en/datasheet/stm32h573ai.pdf
- Pin reference: https://raw.githubusercontent.com/STMicroelectronics/STM32_open_pin_data/master/mcu/STM32H573VITx.xml
Metadata Review
Table
| Field | Current / observed | Assessment |
|---|---|---|
| MPN | STM32H573VIT7 | Correct |
| Manufacturer | STMicroelectronics | Correct |
| Description | Cortex-M33, TrustZone, FPU, 250 MHz, 2 MB Flash, 640 KB RAM, cryptography | Consistent |
| Terminal count | 100 | Correct |
| Footprint pad count | 100 | Correct |
| Datasheet URL | Official ST URL above | Correct; already present |
| Package property | Not populated | Missing; should identify LQFP100 |
| Mount property | Not populated | Missing; should be SMD |
| Logic Function | AND | Incorrect |
| Library subtype | Logic | Inadequate classification for an MCU |
Ordering code interpretation:
V = 100 pins, I = 2 MB Flash, T = LQFP, 7 = industrial -40 to +105 C, LDO supply configuration.Key Specifications
- Arm Cortex-M33 with TrustZone and FPU
- Up to 250 MHz / 375 DMIPS
- 2 MB dual-bank Flash with ECC
- 640 KB SRAM plus 4 KB backup SRAM
- Hardware cryptography including AES/SAES, PKA, HASH/SHA-512, and RNG
- VDD operating range: 1.71 to 3.6 V
- VDDUSB: 3.0 to 3.6 V
- VBAT: 1.2 to 3.6 V
- Temperature grade: -40 to +105 C
- Package: LQFP100, 14 x 14 mm body, 0.50 mm pitch, no exposed pad
Pin and Symbol Cross-Check
All physical pins 1 through 100 exist exactly once in both the symbol and footprint. No duplicate or missing pin/pad numbers were found, and symbol-to-footprint mappings match ST's official pin database. Power and special pins are correctly numbered, including VDD, VSS, VCAP, VDDA/VSSA, VREF+/VREF-, VBAT, VDDUSB, NRST, BOOT0, HSE/LSE, and SWD/JTAG pins.
Symbol mismatches
- All 100 terminals have
Pin Type = Unspecified; power, ground, GPIO, reset, boot, and analog-reference electrical types are not classified. - Pin descriptions are absent for all terminals.
- Pin Group, Section, Terminal Order, and explicit semantic Pin Orientation properties are absent.
- Several special/debug aliases are shortened or omitted:
- Pin 8: PC14-OSC32_IN / OSC32_IN
- Pin 9: PC15-OSC32_OUT / OSC32_OUT
- Pin 12: PH0-OSC_IN
- Pin 13: PH1-OSC_OUT
- Pin 72: PA13 / JTMS / SWDIO
- Pin 76: PA14 / JTCK / SWCLK
- Pin 77: PA15 / JTDI
- Pin 89: PB3 / JTDO / TRACESWO
- Pin 90: PB4 / NJTRST
- GPIO alternate-function descriptions are not included. These omissions do not break physical pin mapping but reduce symbol clarity and ERC usefulness.
Footprint Cross-Check
Current footprint asset:
QFP50P1600X1600X160-100N.kicad_mod.Correct characteristics:
- 100 SMD pads
- 0.50 mm pitch
- 0.30 mm pad width
- 14 x 14 mm package body
- Continuous perimeter numbering
- Pin-1 marker present
- No exposed pad, as expected
Footprint mismatch
ST's Figure 88 land-pattern example specifies approximately 0.30 x 1.20 mm pads, 16.7 x 16.7 mm outer land span, and 14.3 mm inner span. The current footprint uses 0.30 x 1.475 mm pads with a calculated outer span of about 16.951 mm. The pad length is therefore about 0.275 mm longer than ST's example, and the outer span is about 0.251 mm larger.
This should be reviewed before manufacturing. A longer toe/heel land may still be manufacturable, but it is not an exact match to ST's recommended example.
Assets
- Footprint:
QFP50P1600X1600X160-100N.kicad_mod - Symbol:
STM32H573VIT7 Symbol.svg - 3D model:
STM32H573VIT7.stp
The STEP model's exact dimensions and alignment could not be numerically verified from available metadata.
Recommended Corrections
- Replace incorrect
Logic Function = ANDand classify the part as a microcontroller. - Populate Package/Case as LQFP100 and Mount as SMD.
- Assign correct electrical Pin Types to all terminals.
- Add datasheet-derived pin descriptions and special/debug aliases.
- Add consistent Pin Group, Section, Pin Orientation, and Terminal Order metadata.
- Decide whether to revise the footprint to ST's 1.20 mm land length / 16.7 mm outer-span example or retain the current longer lands with an explicit manufacturing rationale.
Result
Metadata Review
Key Specifications
Pin and Symbol Cross-Check
Symbol mismatches
Footprint Cross-Check
Footprint mismatch
Assets
Recommended Corrections
