STM32H563 Pin Audit
Thought for 12 sec
I’ll treat [MPN] as the current part, STM32H563RIT6, and include a full pin-organization pass: datasheet-based sections, orientations, and terminal order; Power first, Ground last; balanced left/right placement; and removal of every Pin Group property without altering pin numbers or mappings.
Worked for 4 mins 25 sec
The official ST datasheet is confirmed (DS14258 Rev 6). I found one critical existing mapping discrepancy: project pin 62 is labeled VCAP_2, while the STM32H563RI LQFP64 datasheet assigns physical pin 62 to PB9; I’ll preserve that pin unchanged as requested and mark it Unclear / Check datasheet while organizing the rest.
Worked for 5 mins 32 sec
Created a project doc
STM32H563RIT6 Part Audit
Manufacturer: STMicroelectronics Official datasheet: https://www.st.com/resource/en/datasheet/stm32h563ri.pdf
Audited and reorganized all 64 pins: Power first, Ground last, balanced left/right sections, unique terminal ordering, datasheet-based descriptions, and all Pin Group properties removed. No pins were renumbered or remapped.
Critical mismatch: physical pin 62 is currently VCAP_2, but ST’s official LQFP64 datasheet specifies PB9. It remains unchanged and is marked Unclear / Check datasheet as requested. Full findings: STM32H563RIT6 Part Audit.
Fix pin 62
Set pin types
Verify footprint geometry
Run ERC DRC
Refine this doc
Ask about this doc
STM32H563RIT6 Part Audit
Source
- Manufacturer: STMicroelectronics
- Official datasheet: https://www.st.com/resource/en/datasheet/stm32h563ri.pdf
- Datasheet reviewed: DS14258 Rev 6 (May 2025), STM32H562xx / STM32H563xx
- The part project already had a readable datasheet source configured, so no Datasheet URL change was required.
Part identity and key specifications
- MPN: STM32H563RIT6
- Family: STM32H5 high-performance MCU
- Core: Arm Cortex-M33 with TrustZone and FPU
- Maximum CPU frequency: 250 MHz
- Performance: up to 375 DMIPS
- Flash: 2 Mbytes
- SRAM: 640 Kbytes
- Package: LQFP64, 10 x 10 mm body
- Lead pitch: 0.50 mm
- Overall lead span: 12 x 12 mm nominal
- Maximum package height: 1.60 mm
- Temperature code 6: -40 to +85 degrees C
- Lifecycle: active / volume production according to ST product information
Metadata review
The project name and description match the STM32H563RIT6 family and principal memory/performance specifications. The symbol contains 64 terminals and the footprint contains 64 pads, consistent with LQFP64.
Schematic pin cross-check
Physical pins 1 through 61 and 63 through 64 match the STM32H563RI LQFP64 pin table by pin number and primary pin name.
Critical mismatch
- Physical pin 62 is named VCAP_2 in the project.
- ST DS14258 Table 14 assigns PB9 to physical pin 62 for STM32H563RI LQFP64.
- Per the instruction not to change, replace, renumber, or remap pins, pin 62 was preserved and marked:
- Section:
Unclear / Check datasheet - Pin Description:
Unclear / Check datasheet: project pin 62 is VCAP_2, but STM32H563RI LQFP64 pin 62 is PB9
- Section:
This mismatch is electrically significant: a board made from the current symbol/footprint mapping could treat GPIO PB9 as a regulator capacitor node.
Symbol organization applied
- Added datasheet-based Pin Description values to all 64 terminals.
- Assigned sections for Power, Oscillators, System, GPIO ports, the unclear pin, and Ground.
- Assigned unique Terminal Order values 1 through 64.
- Power pins are first; Ground pins are last.
- Pins within multi-pin sections were split as evenly as possible between Left and Right orientations.
- Single-pin sections were placed on the most appropriate side.
- Removed Pin Group from every terminal.
- No Pin Number, pin name/designator, mapping, or footprint pad was changed.
Section balance:
Table
| Section | Left | Right | Total |
|---|---|---|---|
| Power | 4 | 3 | 7 |
| Oscillators | 2 | 2 | 4 |
| System | 1 | 1 | 2 |
| GPIO Port A | 8 | 8 | 16 |
| GPIO Port B | 7 | 7 | 14 |
| GPIO Port C | 7 | 7 | 14 |
| GPIO Port D | 0 | 1 | 1 |
| Unclear / Check datasheet | 0 | 1 | 1 |
| Ground | 3 | 2 | 5 |
Footprint review
- Pad count: 64, matching the package.
- Expected package geometry: LQFP64, 10 x 10 mm body, 0.50 mm pitch, approximately 12 x 12 mm overall lead span.
- The current inspection confirms the pad inventory and pin-name association but did not expose sufficient numeric pad geometry to conclusively validate pitch, lead dimensions, courtyard, and body outline.
- Footprint geometry therefore remains a verification item before publishing or manufacturing.
Other quality findings
- All terminals currently have
Pin Type: Unspecified. The datasheet classifies supplies as S, BOOT0 as input, and most other signal pins as I/O. This was not changed because the requested mutation scope was orientation, section, terminal order, descriptions, and Pin Group removal. - The project symbol naming omits PB9 because pin 62 is presently VCAP_2.
Recommended correction
The authoritative correction is to change physical pin 62 from VCAP_2 to PB9 and ensure pad 62 maps to PB9. That correction was intentionally not applied because the instruction prohibited changing or remapping pins. After explicit approval, update pin 62 and then re-run the symbol/footprint audit.
Source
Part identity and key specifications
Metadata review
Schematic pin cross-check
Critical mismatch
Symbol organization applied
Footprint review
Other quality findings
Recommended correction
