Instructions Review and Pinout Report

flux

Terminal labels and properties are updated; I’m verifying the final schematic pins and footprint against the QFN20 datasheet now.

flux

Updated in schematic component:
  • Renamed remaining wrong terminals: PB5 pin 6 -> VCC, VIO33 pin 7 -> PB5, EPAD / Exposed Pad -> EPAD.
  • Set all 21 terminals with datasheet-based Section, Terminal Order, Pin Orientation, Pin Type, and Pin Description.
Terminal Order / Section / orientation changes:
  • Power, order 1: VCC, orientation Top.
  • Reset/Debug, order 2: PC0-NRST, PB6(SWDIO), PA2(SWCLK), orientation Left.
  • Clock, order 3: PC1-OSCIN, PB7-OSCOUT, orientation Left.
  • Communication, orders 4–6: SPI/I2C/USART-capable GPIO pins, orientation Left.
  • GPIO, order 7: PB2, PB0, orientation Left.
  • Ground, order 8: VSS, EPAD, orientation Bottom.
Footprint check result:
  • Matches datasheet QFN20-EP intent: 20 perimeter pads + center exposed pad, 0.4 mm pitch, 3×3 mm body, 1.7×1.7 mm exposed pad.
  • Footprint issue / uncertain: Flux layout also shows 4 extra unnamed internal pad nodes, likely paste/mount sub-pads, but they should be manually confirmed as non-electrical paste features.
Short summary:
  • OK: datasheet pin count and main pad geometry match.
  • Renamed: 3 terminals.
  • Uncertain: EPAD electrical tie to VSS is not explicitly confirmed in extracted datasheet text; 4 unnamed internal footprint pads need manual confirmation.
  • Footprint issue: no blocking mismatch found, only the unnamed internal pads require review.
Fix footprint and review
Fix footprint pads
Verify EPAD connection
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Files

Pins

Symbol

Layout

3D View

PA2(SWCLK)
PA5
PB4
PB1
PA1
PB3
PB5
PA4
PA0
PB6(SWDIO)
PA3
PC1-OSCIN
VSS
PB2
PA6
PC0-NRST
VCC
PA7
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
PC0-NRST
1
Bi-Directional
Reset
Left
2
PC0 GPIO / NRST / option-byte-dependent SWDIO; ADC_IN5, TIM1_CH1N, EVENTOUT
PC1-OSCIN
2
Bi-Directional
Clock
Left
3
PC1 GPIO / OSCIN; SPI_MISO
PB7-OSCOUT
3
Bi-Directional
Clock
Left
3
PB7 GPIO / OSCOUT; SPI_MOSI, TIM14_CH1
VSS
4
Ground
Ground
Bottom
8
Ground supply pin (VSS)
PB6(SWDIO)
5
Bi-Directional
Debug
Left
2
PB6 GPIO / SWDIO; SPI_MISO, ADC_IN6, USART_TX, I2C_SDA
VCC
6
Power In
Power
Top
1
Digital power supply, 1.7 V to 5.5 V
PB5
7
Bi-Directional
Communication
Right
6
PB5 GPIO; SPI_NSS, USART_RX, TIM1_CH3, TIM14_CH1
PB4
8
Bi-Directional
Communication
Right
5
PB4 GPIO; USART_TX, I2C_SDA, TIM1_BKIN
PB3
9
Bi-Directional
Communication
Right
5
PB3 GPIO; USART_CK, I2C_SCL, TIM1_ETR, CMP1_OUT
PB2
10
Bi-Directional
GPIO
Right
7
PB2 GPIO; SPI_SCK, USART_CTS, TIM1_CH1N, TIM1_CH3
PB1
11
Bi-Directional
Communication
Right
6
PB1 GPIO; USART_RTS, ADC_IN0, CMP1_INP/CMP1_INM, TIM1_CH2N, TIM1_CH4, MCO
PB0
12
Bi-Directional
GPIO
Left
7
PB0 GPIO; SPI_SCK, ADC_IN7, CMP1_INM, USART_CK, TIM1_CH2, TIM1_CH3N
PA0
13
Bi-Directional
Communication
Right
4
PA0 GPIO; SPI_MOSI, TIM1_CH1
PA1
14
Bi-Directional
Communication
Right
4
PA1 GPIO; SPI_MISO, TIM1_CH2
PA2(SWCLK)
15
Bi-Directional
Debug
Left
2
PA2 GPIO / SWCLK; USART_RX, I2C_SCL, TIM1_CH4, CMP2_OUT
PA3
16
Bi-Directional
Communication
Left
6
PA3 GPIO; USART_TX, ADC_IN1, CMP2_INP/CMP2_INM, TIM1_CH2
PA4
17
Bi-Directional
Communication
Left
6
PA4 GPIO; USART_RX, ADC_IN2, CMP2_INM, TIM1_CH3, TIM14_CH1
PA5
18
Bi-Directional
Communication
Left
6
PA5 GPIO; USART_CK, TIM1_CH1, TIM14_CH1
PA6
19
Bi-Directional
Communication
Left
4
PA6 GPIO; SPI_NSS, ADC_IN3, external clock in, USART_TX, EVENTOUT
PA7
20
Bi-Directional
Communication
Left
4
PA7 GPIO; SPI_MOSI, ADC_IN4, USART_TX/RX, TIM1_CH4, MCO
EPAD
21
Ground
Ground
Bottom
8
Exposed center pad / thermal pad; present in footprint as pad 21, ground connection not explicitly assigned in extracted datasheet pin table

PY32F002BF15U6TR