Instructions Review and Pinout Report

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Terminal labels and properties are updated; I’m verifying the final schematic pins and footprint against the QFN20 datasheet now.

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Updated in schematic component:
  • Renamed remaining wrong terminals: PB5 pin 6 -> VCC, VIO33 pin 7 -> PB5, EPAD / Exposed Pad -> EPAD.
  • Set all 21 terminals with datasheet-based Section, Terminal Order, Pin Orientation, Pin Type, and Pin Description.
Terminal Order / Section / orientation changes:
  • Power, order 1: VCC, orientation Top.
  • Reset/Debug, order 2: PC0-NRST, PB6(SWDIO), PA2(SWCLK), orientation Left.
  • Clock, order 3: PC1-OSCIN, PB7-OSCOUT, orientation Left.
  • Communication, orders 4–6: SPI/I2C/USART-capable GPIO pins, orientation Left.
  • GPIO, order 7: PB2, PB0, orientation Left.
  • Ground, order 8: VSS, EPAD, orientation Bottom.
Footprint check result:
  • Matches datasheet QFN20-EP intent: 20 perimeter pads + center exposed pad, 0.4 mm pitch, 3×3 mm body, 1.7×1.7 mm exposed pad.
  • Footprint issue / uncertain: Flux layout also shows 4 extra unnamed internal pad nodes, likely paste/mount sub-pads, but they should be manually confirmed as non-electrical paste features.
Short summary:
  • OK: datasheet pin count and main pad geometry match.
  • Renamed: 3 terminals.
  • Uncertain: EPAD electrical tie to VSS is not explicitly confirmed in extracted datasheet text; 4 unnamed internal footprint pads need manual confirmation.
  • Footprint issue: no blocking mismatch found, only the unnamed internal pads require review.
Fix footprint and review
Fix footprint pads
Verify EPAD connection
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Files

Pins

Symbol

Layout

3D View

PY32F002BF15U6TR QFN20 Pinout from Screenshot and Datasheet
Source basis:
  • Screenshot shows a QFN-style 20-pin package with a center exposed pad.
  • Pin-1 orientation dot is visible at the upper-left corner.
  • Datasheet: PUYA PY32F002B, package PY32F002BF15U / QFN20.
Visible physical pins in screenshot
The screenshot shows pins 1–20 around the package plus a center exposed pad marked as pin 21. The visible labels match the PY32F002BF15U QFN20 datasheet pinout.

Table

Screenshot pin / markingDatasheet pin nameMain purposeAlternate / multiplexed functions
1PC0-NRSTGPIO PC0 or reset input, depending option bytesSWDIO, NRST, TIM1_CH1N, EVENTOUT, ADC_IN5
2PC1 / OSCINGPIO PC1, external oscillator inputSPI_MISO, OSCIN
3PB7 / OSCOUTGPIO PB7, external oscillator outputSPI_MOSI, TIM14_CH1, OSCOUT
4VSSGroundPower return / digital ground
5PB6 / SWDIOGPIO PB6, debug data after reset in some option-byte modesSWDIO, SPI_MISO, USART_TX, I2C_SDA, ADC_IN6
6VCCDigital power supply1.7 V to 5.5 V operating supply
7PB5GPIO PB5SPI_NSS, USART_RX, TIM1_CH3, TIM14_CH1
8PB4GPIO PB4USART_TX, I2C_SDA, TIM1_BKIN
9PB3GPIO PB3USART_CK, I2C_SCL, TIM1_ETR, CMP1_OUT
10PB2 / SCKGPIO PB2SPI_SCK, USART_CTS, TIM1_CH1N, TIM1_CH3
11PB1GPIO PB1USART_RTS, TIM1_CH2N, TIM1_CH4, MCO, ADC_IN0, CMP1_INP, CMP1_INM
12PB0GPIO PB0SPI_SCK, USART_CK, TIM1_CH2, TIM1_CH3N, ADC_IN7, CMP1_INM
13PA0GPIO PA0SPI_MOSI, TIM1_CH1
14PA1GPIO PA1SPI_MISO, TIM1_CH2
15PA2 / SWCLKGPIO PA2, debug clock after resetUSART_RX, I2C_SCL, SWCLK, TIM1_CH4, CMP2_OUT
16PA3GPIO PA3USART_TX, TIM1_CH2, ADC_IN1, CMP2_INP, CMP2_INM
17PA4GPIO PA4USART_RX, TIM1_CH3, TIM14_CH1, ADC_IN2, CMP2_INM
18PA5GPIO PA5USART_CK, TIM1_CH1, TIM14_CH1
19PA6GPIO PA6SPI_NSS, USART_TX, EVENTOUT, ADC_IN3, external clock input
20PA7GPIO PA7SPI_MOSI, USART_TX, USART_RX, TIM1_CH4, MCO, ADC_IN4
21Exposed pad / EPCenter thermal/mechanical pad visible in screenshotNot listed as a functional signal pin in the extracted datasheet pin table; normally connect per package/datasheet layout guidance, often to ground if specified by manufacturer

Table

PinNameFunction
4VSSGround
6VCCDigital supply, 1.7 V to 5.5 V
21EPExposed pad; mechanical/thermal pad, electrical connection should follow package guidance
Communication and debug interface pins
SPI

Table

FunctionAvailable pins
SPI_MOSIPA0 pin 13, PA7 pin 20, PB7 pin 3
SPI_MISOPA1 pin 14, PB6 pin 5, PC1 pin 2
SPI_SCKPB0 pin 12, PB2 pin 10
SPI_NSSPA6 pin 19, PB5 pin 7
UART / USART

Table

FunctionAvailable pins
USART_TXPA3 pin 16, PA6 pin 19, PA7 pin 20, PB4 pin 8, PB6 pin 5
USART_RXPA2 pin 15, PA4 pin 17, PA7 pin 20, PB5 pin 7
USART_CKPA5 pin 18, PB0 pin 12, PB3 pin 9
USART_CTSPB2 pin 10
USART_RTSPB1 pin 11
I2C

Table

FunctionAvailable pins
I2C_SCLPA2 pin 15, PB3 pin 9
I2C_SDAPB4 pin 8, PB6 pin 5
SWD debug

Table

FunctionAvailable pins / notes
SWCLKPA2 pin 15
SWDIOPB6 pin 5 or PC0 pin 1 depending option-byte configuration
Unclear or configuration-dependent items
  • The screenshot text is small; PB6-SWD and PA2-SWC/SWCLK can be visually confused. Datasheet confirms PB6 is SWDIO/SWD and PA2 is SWCLK/SWC.
  • PC0 pin 1 may be PC0 GPIO, NRST, or SWDIO depending option-byte configuration.
  • SWDIO location is configuration-dependent: PB6 or PC0, controlled by option bytes.
  • The center exposed pad is visible as pin 21 in the screenshot, but the extracted datasheet pin-definition table does not assign it a signal function. Verify the package land pattern note before deciding whether to tie it to VSS.
  • No CAN-bus or RS-485 peripheral pins are listed for this MCU in the extracted datasheet data; those interfaces would require external controllers/transceivers or firmware protocols over available GPIO/UART/SPI as applicable.

  • Visible physical pins in screenshot

  • Power-related pins

  • Communication and debug interface pins

  • SPI

  • UART / USART

  • I2C

  • SWD debug

  • Unclear or configuration-dependent items