Part Verification and Datasheet Update

flux

Completed the part review and created the detailed findings in Part Verification Report.
Summary: the datasheet URL was already set, the symbol pin names/numbers match the PIC16F84A-20I/P datasheet, but pin types/descriptions are missing and the footprint is still placeholder geometry rather than a valid 18-pin 300 mil PDIP footprint.
A

adrian95

Fix the pin types, add pin descriptions, set PDIP package metadata, and build the correct footprint.

flux

I’ll update the terminal metadata from the datasheet, set the PDIP package property cleanly, then replace the placeholder pads with a proper 18-pin 300 mil PDIP footprint and verify it.

flux

I found the package property is already set to 18-PDIP; now I’m applying datasheet-backed pin metadata and parametric DIP footprint rules.

flux

Pin metadata is corrected and the footprint rules are applied; I’m doing a final schematic/layout readback now.

flux

Done.
  • Updated all 18 terminal pin types to Flux-standard values and added datasheet-backed pin descriptions.
  • Verified project package metadata is set to Package or Case Code = 18-PDIP.
  • Built the correct 18-pin 300 mil DIP footprint with 2.54 mm pitch, 7.62 mm row spacing, through-hole pads, and rectangular pin-1 marker.
  • Verified the schematic metadata and layout footprint rules by readback.
Open item: the generated footprint asset uses 0.76 mm drills / 1.16 mm pads internally, while the explicit pad rules are set to 0.8 mm drills; if you want a different house-standard DIP pad stack, I can tune that next.
Tune pads and review
Tune DIP pads
Run ERC/DRC
Update review report
Check footprint dimensions
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Part Type
Pin Description
Terminal Order
RA2
1
Bi-Directional
Terminal
PORTA bit 2 bidirectional I/O, TTL input buffer.
RA3
2
Bi-Directional
Terminal
PORTA bit 3 bidirectional I/O, TTL input buffer.
RA4/T0CKI
3
Bi-Directional
Terminal
PORTA bit 4 bidirectional I/O with Schmitt trigger input; Timer0 clock input; output is open-drain.
~MCLR
4
Input
Terminal
Master Clear reset input and programming voltage input; active-low reset.
VSS
5
Ground
Terminal
Ground reference for logic and I/O pins.
RB0/INT
6
Bi-Directional
Terminal
PORTB bit 0 bidirectional I/O; external interrupt input when configured as RB0/INT.
RB1
7
Bi-Directional
Terminal
PORTB bit 1 bidirectional I/O, TTL input buffer; PORTB supports software-programmed weak pull-ups on inputs.
RB2
8
Bi-Directional
Terminal
PORTB bit 2 bidirectional I/O, TTL input buffer; PORTB supports software-programmed weak pull-ups on inputs.
RB3
9
Bi-Directional
Terminal
PORTB bit 3 bidirectional I/O, TTL input buffer; PORTB supports software-programmed weak pull-ups on inputs.
RB4
10
Bi-Directional
Terminal
PORTB bit 4 bidirectional I/O; interrupt-on-change pin.
RB5
11
Bi-Directional
Terminal
PORTB bit 5 bidirectional I/O; interrupt-on-change pin.
RB6
12
Bi-Directional
Terminal
PORTB bit 6 bidirectional I/O; interrupt-on-change pin; ICSP serial programming clock.
RB7
13
Bi-Directional
Terminal
PORTB bit 7 bidirectional I/O; interrupt-on-change pin; ICSP serial programming data.
VDD
14
Power In
Terminal
Positive supply for logic and I/O pins.
OSC2/CLKOUT
15
Output
Terminal
Oscillator crystal output; connects to crystal/resonator in crystal oscillator mode; CLKOUT in RC mode at one-quarter OSC1 frequency.
OSC1/CLKIN
16
Input
Terminal
Oscillator crystal input or external clock source input; Schmitt trigger in RC mode, CMOS input otherwise.
RA0
17
Bi-Directional
Terminal
PORTA bit 0 bidirectional I/O, TTL input buffer.
RA1
18
Bi-Directional
Terminal
PORTA bit 1 bidirectional I/O, TTL input buffer.

PIC16F84A-20I/P