• Datasheet URL mutation: Not performed. The exact project property Datasheet URL was already populated, so the requested conditional mutation was not applicable.
• Stored datasheet: The current uploaded PDF resolves and identifies itself as official Microchip DS00003672A (Rev. A, 10/2020). It explicitly covers PD70211ILQ-TR and the QFN-36 package.
• Latest official source used for audit: DS00003672B (Rev. B, 09/2021). Rev. B specifically updated Figure 4-1, Table 4-1, and the Recommended PCB Layout section (Rev. History, p. 36).
• Terminal accounting: 37/37 terminals are present: perimeter pins 1–36 plus exposed pad 37.
• Footprint accounting: 37/37 copper pads are present and mapped by terminal identity.
• Geometry mutation: None. Symbol pins and footprint geometry were not altered.

• Ordering P/N: PD70211ILQ-TR; RoHS compliant, Pb-free; ambient rating –40 °C to +85 °C; QFN-36, 6 mm × 6 mm, 0.5 mm pitch (Table 6-1, p. 34).
• Function: PoE Powered Device interface/controller with integrated current-mode PWM regulator control. Supports IEEE 802.3af/at, HDBaseT, UPoE/general 2-pair and 4-pair configurations, programmable classification, 2/3/4/6-event classification, wall-adapter operation, integrated 0.3 Ω isolation FET, inrush limiting, and synchronous flyback/active-clamp-forward/buck/boost control (Product Overview and Features, pp. 1–2).

• 36-terminal QFN plus exposed pad; body 6.00 mm × 6.00 mm BSC; pitch 0.50 mm BSC; height 0.80–1.00 mm (0.90 mm nominal); package terminal width 0.20–0.30 mm; package terminal length 0.45–0.65 mm; exposed pad 4.00–4.20 mm each axis (4.10 mm nominal); terminal-to-EP clearance 0.40 mm REF (Figure 4-1 and Table 4-1, pp. 22–23).
• EPAD is electrical pin 37 and must connect to the VPN_IN PCB plane (Table 3-1, p. 21).

• Front-end operating VPP: 0–57 V; ambient –40 °C to +85 °C, corresponding maximum operating junction 125 °C (Table 2-2, p. 8).
• Absolute maximum VPP/VPN_OUT/RDET: –0.3 to 74 V; junction –40 °C to +150 °C; storage –65 °C to +150 °C, MSL3 (Table 2-1, p. 7).
• PWM VCC operating range: 7.8–20 V; programmable switching range 100–500 kHz; synchronization input 200–1000 kHz; maximum duty-cycle operating rating 44.5% (Table 2-3, p. 8).
• Isolation FET: 0.3 Ω max; inrush current limit 105/240/325 mA min/typ/max; continuous load 2 A max; OCP 2.2 A min (Table 2-5, pp. 9–10).
• Front-end UVLO: ON 36–42 V, OFF 30.5–34.5 V (Table 2-5, pp. 9–10).
• PWM reference/VINS threshold: 1.200 V typ; differential voltage amplifier gain 7 typ; current-sense amplifier gain 5 typ; thermal shutdown 157 °C typ, hysteresis 15–30 °C (Table 2-7, pp. 12–14).
• Thermal resistance on the stated JESD-51 four-layer board: θJA 22.3 °C/W, θJP 3 °C/W, θJC 4 °C/W (Table 2-4, p. 8).

• All 37 terminal objects have unique pin numbers 1–37 and explicit symbol pin positions.
• The parametric arrangement groups pins around four sides and is logically complete.
• The current direct part-project image/flat render returned blank, and get_symbol could not resolve a version because the newly created part has no project history commit. Therefore visual text-overlap/body-shape verification is unresolved, although the terminal metadata and positions were fully inspected.
• No terminal has Pin Description, Pin Group, Pin Orientation, Section, or Terminal Order metadata; only Symbol Pin Position, Pin Number, and Pin Type=Unspecified were observed.

• Pads: 37 total: pads 1–36 around the perimeter, 9 per side, plus center pad 37.
• Pitch: 0.50 mm on all four sides.
• Perimeter lands: rectangular 0.30 mm × 1.00 mm; centers at ±2.85 mm from package center, with coordinates at –2.0 to +2.0 mm in 0.5 mm steps.
• Center EP land: 4.20 mm × 4.20 mm, centered at (0,0), mapped to terminal EP / pin 37.
• Body/fabrication outline: 6.00 mm × 6.00 mm; pin-1 chamfer shown in fabrication outline.
• Courtyard: 7.20 mm × 7.20 mm.
• Pin-1 marker: circle at approximately (–3.35, –2.75) mm; pad 1 is on the left side nearest the lower-left corner in the footprint coordinate system. Numbering then proceeds counter-clockwise around the package: 1–9 left, 10–18 top, 19–27 right, 28–36 bottom. This is consistent with the top-view QFN convention in Figure 3-1/Figure 4-1.

• Package body, lead count, pitch, and EP size are consistent with Table 4-1 (pp. 22–23).
• The 0.30 mm land width is at the maximum package-terminal width and the 1.00 mm land length extends beyond the 0.45–0.65 mm package lead, which is a plausible solder land rather than a package-lead copy.
• Rev. B’s recommended layout is shown in Figures 4-2 through 4-5 (pp. 24–27), based on IPC7093A October 2020. The datasheet explicitly notes a 5 mil stencil and 0.05 mm radius on all paste openings (Figure 4-4, p. 26).
• The current footprint places F.Paste over the entire 4.20 mm × 4.20 mm exposed pad as one opening. This does not reproduce the datasheet’s dedicated patterned paste-mask figure and creates a likely assembly risk (excess solder, package float, and voiding).
• No thermal-via array is encoded in the footprint. Because EPAD must connect to the VPN_IN plane and thermal performance depends strongly on PCB construction, the recommended copper/via implementation should be confirmed from Figures 4-2 through 4-5 before manufacturing.
• OCR extraction did not recover all dimension callouts embedded in Figures 4-2 through 4-5. Exact recommended solder-mask expansion, paste-window dimensions/coverage, and via pattern remain unresolved and require visual/mechanical reading of those figures.

1. All 37 symbol terminals have Pin Type=Unspecified. This prevents meaningful electrical-rule checking and fails the requested electrical pin-type fidelity against the datasheet.
2. Exposed-pad paste aperture is a single full-size 4.20 mm square. Rev. B provides a patterned recommended paste mask (Figure 4-4, p. 26); the current full-area paste definition is a manufacturing risk and should be reviewed before use.

1. All 37 terminals lack pin descriptions. Datasheet Table 3-1 provides authoritative descriptions on pp. 16–21.
2. Stored Datasheet URL points to older Rev. A rather than latest official Rev. B. It is still an official, applicable datasheet, and the task permitted URL mutation only when absent; therefore it was intentionally not changed.
3. No thermal-via pattern is included for EPAD. Exact requirements must be confirmed from the recommended-layout figures and the target PCB stackup/thermal design.
4. Exact recommended land-pattern conformance is unresolved. The current 0.30 mm × 1.00 mm perimeter lands and 4.20 mm EP are nominally plausible, but image-embedded dimensions from Figures 4-2–4-5 were not machine-extractable.
5. Rendered symbol could not be visually validated because the direct render was blank and the part has no resolvable history version for get_symbol.

1. Pin 37 is named EP rather than datasheet EPAD.
2. Duplicate-function pins are named VPN_IN_1, VPN_IN_2, VPN_OUT_1, and VPN_OUT_2 rather than preserving identical datasheet designators.
3. The broad Integrated Circuits type is valid but not as specific as PoE PD/power-management controller.
4. Manufacturer naming changed historically from Microsemi to Microchip Technology; the current Microchip Technology value is appropriate for the official 2021 datasheet.

• Exact numeric callouts in recommended-layout Figures 4-2 through 4-5 (solder-mask expansion, paste-window geometry/coverage, and thermal-via details) require manual visual extraction from the PDF artwork.
• 3D STEP body/lead seating and dimensions were not independently measured.
• Symbol visual quality could not be confirmed with the current rendering endpoint; metadata completeness was confirmed instead.

1. Microchip Technology, PD70211 — PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications, DS00003672B, Rev. B, September 2021: https://ww1.microchip.com/downloads/aemDocuments/documents/POE/ProductDocuments/DataSheets/PD70211_PD_Controller_with_Switching_Regulator_Datasheet_DS00003672B.pdf
2. Pin Configuration, Figure 3-1 and Table 3-1, pp. 16–21.
3. Package Specifications, Figure 4-1 and Table 4-1, pp. 22–23.
4. Recommended PCB Layout, Figures 4-2 through 4-5, pp. 24–27.
5. Ordering Information, Table 6-1, p. 34.
6. Revision History, p. 36.