Part Datasheet Audit

A

adrian95

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

flux

I’ll audit the part metadata, source the official datasheet if needed, update the Datasheet property, then verify the symbol, footprint, and pin descriptions against it.

flux

Audit complete. Added the official NXP datasheet, verified all 17 terminals, and corrected the symbol pin names/types/descriptions and HLQFN16/SOT1688-3 footprint geometry.
  • Key specs: dual-axis XY medium-g accelerometer, ±15.5 g to ±150 g, SPI/DSI3 interfaces, −40°C to +125°C, 4 × 4 × 1.45 mm wettable-flank package, 0.8 mm pitch.
  • Corrected mismatches: pins 11, 12, 14, and 17; functional pin grouping; oversized/offset footprint lands.
  • Open item: copper geometry is verified, but solder-paste apertures should be optimized for the assembler’s stencil process. The imported footprint filename still misleadingly references a 5.15 mm outline.
Fix paste and verify
Optimize paste apertures
Rename footprint asset
Run final review
Export verified part
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Files

Pins

Symbol

Layout

3D View

PCM1/ARM1
Pin Number
2
TEST1
Pin Number
4
SCLK/SCL
Pin Number
9
MISO/SDA
Pin Number
11
VCC_1
Pin Number
1
MOSI
Pin Number
10
PCM0/ARM0
Pin Number
12
TEST0
Pin Number
3
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
VCC_1
1
Power In
Power
Power
Top
1
Supply; NXP recommends connection to VCC, but this pin may optionally be left unterminated.
PCM1/ARM1
2
Output
Sensor Outputs
Sensor Outputs
Left
2
Multiplexed channel 1 PCM digital output or configurable channel 1 arming output.
TEST0
3
Passive
Test
Test
Left
3
Test pin; leave unterminated as recommended, or optionally tie to VSS.
TEST1
4
Passive
Test
Test
Left
3
Test pin; leave unterminated as recommended, or optionally tie to VSS.
TEST2
5
Passive
Test
Test
Left
3
Test pin; leave unterminated as recommended, or optionally tie to VSS.
TEST3
6
Passive
Test
Test
Left
3
Test pin; leave unterminated as recommended, or optionally tie to VSS.
VSS
7
Ground
Ground
Ground
Bottom
10
Supply return node.
SS_B
8
Input
Serial Interface
Serial Interface
Right
4
SPI slave-select input with internal pull-up; in I2C mode pull up externally to VBUF.
SCLK/SCL
9
Input
Serial Interface
Serial Interface
Right
4
SPI serial-clock or I2C serial-clock input; I2C mode requires an external pull-up to VBUF.
MOSI
10
Input
Serial Interface
Serial Interface
Right
4
SPI serial-data input with internal pull-down; leave unterminated or optionally tie to VSS in I2C mode.
MISO/SDA
11
Bi-Directional
Serial Interface
Serial Interface
Right
4
SPI serial-data output or I2C serial-data input/output; I2C mode requires an external pull-up to VBUF.
PCM0/ARM0
12
Output
Sensor Outputs
Sensor Outputs
Left
2
Multiplexed channel 0 PCM digital output or configurable channel 0 arming output.
VCC_2
13
Power In
Power
Power
Top
1
Device supply; connect an external capacitor between this pin and VSS.
VSS_2
14
Ground
Ground
Ground
Bottom
10
Supply return node.
VCC_4
15
Power In
Power
Power
Top
1
Device supply; connect an external capacitor between this pin and VSS.
VCC_5
16
Power In
Power
Power
Top
1
Device supply; connect an external capacitor between this pin and VSS.
PAD
17
Ground
Ground
Ground
Bottom
10
Exposed die-attach pad; must be connected to VSS.

NXLS95322AESR2