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Part Audit Report
Scope
Audit of MFS2633AMDA0AD metadata, schematic symbol, PCB footprint, and pin descriptions against NXP's official FS26 short data sheet, FS26_SDS Rev. 6.1 (30 July 2026).
Official NXP datasheet: https://www.nxp.com/docs/en/data-sheet/FS26_SDS.pdf
Metadata review

Table

FieldProject/library valueDatasheet / official sourceResult
MPNMFS2633AMDA0ADMFS2633AMDA0ADMatch
ManufacturerNXP USA Inc. / NXPNXP SemiconductorsMatch; naming variation only
DescriptionPower Management Specialized - PMIC Safety System Basis Chip with Low Power for ASIL D, LQFP-48 trayFS26 safety system basis chip with low power for ASIL D/ASIL BSubstantively correct
Package48-LQFP-EP (7x7); library search also shows 48-LQFP7.0 x 7.0 mm, 48-pin HLQFP/LQFP exposed-pad, 0.5 mm pitch, SOT1571-6Project metadata matches; published library package text should explicitly retain EP and 7x7
Pin/pad count4948 perimeter pins plus exposed pad EP pin 49Match
Datasheet URLAlready populated with an uploaded NXP FS26 datasheet PDFOfficial direct URL abovePresent; no update required under the requested rule
Part TypeIntegrated CircuitsPMIC / automotive safety system basis chipBroad but acceptable
IC subtype / logic functionLogic / AND in library search metadataPMIC / system basis chipIncorrect classification
Lifecycle guidanceNot setRelease version A is no longer recommended for new designs; comparable H release is recommendedMissing important lifecycle note
Key specifications
  • Automotive power system basis chip developed for ISO 26262 systems up to ASIL D.
  • MFS2633...D variant: 1.65 A VCORE class, two tracking regulators, FS1B, long-duration timer, ASIL D feature set, blank OTP engineering-development variant.
  • 40 V DC maximum input capability.
  • Operation down to 3.2 V battery with VBST used at the front end; down to 6 V without front-end VBST.
  • VPRE synchronous buck: up to 1.5 A.
  • VCORE synchronous buck: up to 1.65 A for FS2633, configurable 0.8 V to 3.35 V.
  • LDO1 and LDO2: selectable 3.3 V or 5.0 V, up to 400 mA each.
  • TRK1 and TRK2: up to 150 mA each.
  • VREF accuracy: 0.75%.
  • Ambient operating range: -40 C to +125 C; junction range to +150 C.
  • Package: SOT1571-6 / HLQFP48, 7 x 7 mm body, 0.5 mm pitch, exposed thermal pad.
Schematic symbol cross-check
All pin numbers 1 through 49 are represented exactly once, and the number-to-function mapping is correct except for naming text issues below.
Pin-name mismatches

Table

PinSymbol nameDatasheet nameAssessment
2WAKE_2WAKE2Minor naming mismatch; remove underscore
14VMONTEXTVMONEXTTypographical error; symbol adds a T
38N.C.NCCosmetic naming variation
Pin metadata deficiencies
  • Every terminal has Pin Type: Unspecified. The datasheet defines analog input/output, digital input/output, ground, and not-connected types for all pins.
  • No terminal has a Pin Description property. The datasheet provides a description for every pin.
  • EP pin 49 should be typed as ground/power and described as the exposed pad that must be connected to ground.
  • Pin 38 should be typed as not connected.
These omissions reduce ERC quality and make the symbol less self-documenting even though the numerical pinout is correct.
Footprint cross-check
Footprint asset: QFP50P900X900X160-49N.kicad_mod.
Matches
  • 48 perimeter pads plus central exposed pad = 49 total pads.
  • 0.5 mm perimeter-pad pitch.
  • 7 x 7 mm package-body fabrication outline.
  • Approximately 9 x 9 mm lead span, consistent with the package family.
  • Pin-1 marker and counter-clockwise QFP numbering are consistent with the symbol pin numbering.
Potential mismatch requiring correction/confirmation
  • The central PCB pad is 5.2 x 5.2 mm, while the NXP package exposed metal pad is specified as approximately 4.4 to 4.5 x 4.4 to 4.5 mm. NXP provides dedicated PCB solder-mask, solderable-area, and stencil guidance in FS26_SDS Figures 59-61. A land pad larger than the component EP may be intentional, but 5.2 mm should be checked directly against those figures before production.
  • The footprint uses one solid paste opening for the full EP. For a large exposed pad, segmented paste apertures are commonly required; NXP's Figure 61 should be followed. The imported footprint does not encode that segmented stencil pattern.
  • No thermal-via pattern is included in the footprint asset. Thermal vias may be added at board level, but the design must ensure EP-to-ground thermal connection.
  • Footprint naming says 1.60 mm height, while NXP identifies SOT1571-6 as a 1.5 mm-body HLQFP48. This is a naming/3D-envelope discrepancy to verify, not a pad-pinout error.
Overall verdict
Electrical pin mapping: Pass with two pin-label corrections. All 49 pin numbers map to the correct functions.
Symbol metadata: Fail for completeness. Pin types and pin descriptions are absent for every terminal.
Footprint: Provisionally acceptable for perimeter geometry, but the EP copper/paste implementation needs manufacturer-guideline verification before fabrication.
Part metadata: Mostly correct, but the Logic / AND classification is wrong and release-A lifecycle guidance is missing.
  1. Rename pin 2 to WAKE2 and pin 14 to VMONEXT; optionally normalize pin 38 to NC.
  2. Populate pin types and datasheet-derived descriptions for all 49 terminals.
  3. Change IC subtype/classification from Logic/AND to PMIC / Safety System Basis Chip.
  4. Verify and revise the exposed-pad copper, solder-mask, and paste geometry using FS26_SDS Figures 59-61; add a thermal-via strategy in the board design.
  5. Add a lifecycle note that release version A is not recommended for new designs and the comparable H-release part is preferred.

  • Scope

  • Metadata review

  • Key specifications

  • Schematic symbol cross-check

  • Pin-name mismatches

  • Pin metadata deficiencies

  • Footprint cross-check

  • Matches

  • Potential mismatch requiring correction/confirmation

  • Overall verdict

  • Recommended fixes