LSM6DS3TR C Review

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Updated and verified all pins.
  • Generalized groups: Power, Ground, Interface, Digital I/O, Other
  • Added/updated Section on every pin to exactly match its Pin Group
  • Kept the one-pin-one-group rule intact; no pin is assigned to multiple groups.
A

adrian95

Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.

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I’ll assign terminal ordering and orientations by group, keeping Power at order 1/top and Ground at order 10/bottom, with the remaining groups split across left/right.

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Assigned and verified Terminal Order and Pin Orientation.
  • Power: order 1, orientation Top
  • Interface: order 2, orientation Left
  • Digital I/O: order 3, orientation Right
  • Other: order 9, orientation Right
  • Ground: order 10, orientation Bottom
Note: there are three remaining non-power/non-ground groups but only two allowed remaining orientations (Left/Right), so Other shares Right with Digital I/O while the left/right distribution requirement is still met.
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Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
ADO/SA0
1
Bi-Directional
Interface
Interface
Left
2
SDO/SA0: SPI 4-wire serial data output; I2C address least-significant bit selector.
SDX
2
Bi-Directional
Interface
Interface
Left
2
Mode 1: connect to VDDIO or GND. Mode 2: I2C master serial data (MSDA).
SCX
3
Bi-Directional
Interface
Interface
Left
2
Mode 1: connect to VDDIO or GND. Mode 2: I2C master serial clock (MSCL).
INT1
4
Output
Digital I/O
Digital I/O
Right
3
Programmable interrupt output 1.
VDDIO
5
Power In
Power
Power
Top
1
I/O power supply VDDIO; place 100 nF ceramic decoupling capacitor near pin.
GND_1
6
Ground
Ground
Ground
Bottom
10
0 V supply ground.
GND_2
7
Ground
Ground
Ground
Bottom
10
0 V supply ground.
VDD
8
Power In
Power
Power
Top
1
Core power supply VDD; place 100 nF ceramic decoupling capacitor near pin.
INT2
9
Bi-Directional
Digital I/O
Digital I/O
Right
3
Programmable interrupt output 2; data enable (DEN); in Mode 2 also I2C master external synchronization (MDRDY).
NC_1
10
Not Connected
Other
Other
Right
9
Leave electrically unconnected and soldered to PCB.
NC_2
11
Not Connected
Other
Other
Right
9
Leave electrically unconnected and soldered to PCB.
CS
12
Input
Interface
Interface
Left
2
I2C/SPI mode selection and SPI chip select: high enables I2C / SPI idle, low selects SPI.
SCL
13
Input
Interface
Interface
Left
2
I2C serial clock (SCL); SPI serial port clock (SPC).
SDA
14
Bi-Directional
Interface
Interface
Left
2
I2C serial data (SDA); SPI serial data input (SDI); 3-wire SPI serial data output (SDO).

LSM6DS3TR-C